• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.24 no.4
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• pp.43-47
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• 2024

This paper introduces a phased-array single-channel transceiver beamformer IC built using 65nm CMOS technology, covering the 8-16 GHz range and targeting the X and Ku bands for radar and satellite communications. Each signal path in the IC features a low noise amplifier (LNA), power amplifier (PA), phase shifter (PS), and variable gain amplifier (VGA), which allow for phase and gain adjustments essential for beam steering and tapering control in typical beamforming systems. Test results show that the phase-compensated VGA offers a gain range of 15 dB with 0.25 dB increments and an RMS gain error of 0.27 dB. The active vector modulator phase shifter delivers a 360° phase range with 2.8125° steps and an RMS phase error of 3.5°.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.1
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• pp.48-55
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• 2017

This paper proposes a new link structure that transmits power, clock, and data through a single optical fiber for a future automotive network. A pulse-position modulation (PPM) technique is adopted to guarantee a DC-balanced signal for robust power transmission regardless of transmitted data pattern. Further, circuit implementations and theoretical analyses for the proposed PPM transceiver are described in this paper. A prototype transceiver fabricated in 65-nm CMOS technology, is used to verify the PPM signaling part of the proposed system. The prototype achieves a $10^{-13}$ bit-error rate and 0.188-UI high frequency jitter tolerance while consuming 14 mW at 800 Mb/s.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.129-132
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• 2000

In this paper, a 1.8㎓ low noise amplifier was designed and simulated using 0.2$\mu\textrm{m}$ Si CMOS process. Noise characteristics and s parameters were extracted for the 300$\mu\textrm{m}$ gate width and 0.25$\mu\textrm{m}$ gate length NMOS transistors. For high available power gain, each stage was designed cascode type. It revealed available power gain of 23.5dB, noise figure of 2.0dB, power consumption of 15㎽ at 2.5V. It was shown that designed low noise amplifier had good RF performance. Designed Si CMOS LNA is expected to be used for RF front-end in transceiver.

• Journal of Navigation and Port Research
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• v.36 no.9
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• pp.737-740
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• 2012

A miniaturized CMOS bandpass filter for a single RF transceiver system is presented, using diagonally end-shorted coupled lines and lumped capacitors. In contrast to conventional miniaturized coupled line filters, it is proven that the effective permittivity variation of the coupled transmission line has no effect on shifting the center frequency when the bandpass filter is highly miniaturized. A bandpass filter at a center frequency of 2 GHz was fabricated by $0.18{\mu}m$ CMOS technology. The insertion loss with the die area of $1500{\mu}m{\times}1000{\mu}m$ is -5.14 dB. Simulated results are well agreed with the easurements. It also verify the center frequency stability in the compact size bandpass filter.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.9
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• pp.11-17
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• 2004

This paper describes the implementation of monolithic optical transceiver circuitry being used as a part of the fiber optic modules. It has been fabricated in 0.6 ${\mu}{\textrm}{m}$ 2-poly 3-metal silicon CMOS analog technology and operates at 155.52 Mbps(STM-1) data rates. It drives laser diode to transmit intensity modulated optical signal according to 155.52 Mbps electrical data from system. Also, it receives 155.52 Mbps optical data that transmitted from other systems and converts it to electrical data using photo diode and amplifier. To avoid noise and interference between transmitter and receiver on one chip, layout techniques such as special placement, power supply separation, guard ring, and protection wall were used in the design. The die area is 4 ${\times}$ 4 $\textrm{mm}^2$, and it has 32.3 ps rms and 335.9 ps peak to peak jitter on loopback testing. the measured power dissipation of whole chip is 1.15 W(230 mW) with a single 5 V supply.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.8A
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• pp.1252-1258
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• 1999

This paper describes a COMS IF transceiver IC for 10-MHz bandwidth wireless local loops. It interfaces between the RF section and the digital MODEM section and performs the IF-to-baseband (Rx) and baseband-to-IF (Tx) frequency conversions. The chip incorporates variable gain amplifiers, phase-locked loops, low pass filters, analog-to-digital and digital-to-analog converters. It has been implemented in a 0.6 -${\mu}{\textrm}{m}$ 2-poly 3-metal CMOS process. The phase-locked loops include voltage-controlled oscillators, dividers, phase detectors, and charge pumps on chip. The only external complonents are the filter and the varactor-tuned LC tank circuit. The chip size is 4 mm $\times$ 4 mm and the total supply current is about 57 mA at 3.3 V.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.791-794
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• 2003

The increasing computational capability of processors is driving the need for high bandwidth links to communicate and store the information that is processed. Such links are often an important part of multi processor interconnection, processor-to-memory interfaces and Serial-network interfaces. This paper describes a 0.11-${\mu}{\textrm}{m}$ CMOS 4 Gbp s/pin 3-Level transceiver using RSL/(Rambus Signaling Logic) for high bandwidth. This system which uses a high-gain windowed integrating receiver with wide common-mode range which was designed in order to improve SNR when operating with the smaller input overdrive of 3-Level. For multi-gigabit/second application, the data rate is limited by Inter-Symbol Interference (ISI) caused by low pass effects of channel, process-limited on-chip clock frequency, and serial link distance. In order to detect the transmited 4Gbps/pin with 3-Level data sucessfully ,the receiver is designed using 3-stage sense amplifier. The proposed transceiver employes multi-level signaling (3-Level Pulse Amplitude Modulation) using clock multi phase, double data rate and Prbs patten generator. The transceiver shows data rate of 3.2 ~ 4.0 Gbps/pin with a 1GHz internal clock.

• Journal of IKEEE
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• v.27 no.1
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• pp.12-18
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• 2023

The current circuit technology that individually connects each qubit to a control circuit at room temperature has limitations in achieving scalability and reliability of a quantum computer. With the advent of cryogenic CMOS interconnect electronics, it is expected to dramatically improve the interconnect complexity, system reliability and size, and price. In this paper, we introduce the CMOS integrated sensing and control technology platform overcoming the problems caused by the fragile and sensitive characteristics of qubit.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.4
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• pp.49-58
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• 2014

A low-swing differential near-ground signaling (NGS) transceiver for low-power high-speed mobile I/O interface is presented. The proposed transmitter adopts an on-chip regulated programmable-swing voltage-mode driver and a pre-driver with asymmetric rising/falling time. The proposed receiver utilizes a new multiple gain-path differential amplifier with feed-forward capacitors that boost high-frequency gain. Also, the receiver incorporates a new adaptive bias generator to compensate the input common-mode variation due to the variable output swing of the transmitter and to minimize the current mismatch of the receiver's input stage amplifier. The use of the new simple and effective impedance matching techniques applied in the transmitter and receiver results in good signal integrity and high power efficiency. The proposed transceiver designed in a 65-nm CMOS technology achieves a data rate of 13 Gbps/channel and 0.3 pJ/bit (= 0.3 mW/Gbps) high power efficiency over a 10 cm FR4 printed circuit board.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.45 no.7
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• pp.38-44
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• 2008

In this paper, we introduce an low complexity and low power IR-UWB (impulse radio ultra wideband) baseband transceiver for wireless sensor network. The proposed baseband, implemented by TSMC 0.18um CMOS technology, has a simple structure in which a simplified packet structure and a digital synchronizer with 1-bit sampler to detect incoming pulses are used. Besides, clock gating method using gated clock cell as well as customized clock domain division can reduce the total power consumption drastically. As a result, the proposed baseband has about 23K digital gates with an internal memory of 2Kbytes and achieves about 1.8mW@1Mbps power consumption.