• Proceedings of the IEEK Conference
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• 대한전자공학회 2003년도 신호처리소사이어티 추계학술대회 논문집
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• pp.517-520
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• 2003

Commercial video scope use CCD sensor and frame grabber for image capture and A/D interface but application limited by input resolution and high cost. In this paper we introduce portable video scope using CMOS sensor, USB pen and tuner card (low frame grabber) in place of commercial CCD sensor and frame grabber. Our video scope serves as an essential link between advancing commercial technology and research, providing cost effective solutions for educational, engineering and medical applications across an entire spectrum of needs. The software implementation is done using Direct Show in second version after initial trials using First version VFW (video for window), which gave very low frame rate. Our video scope operates on windows 98, ME, XP, 2000. The drawback of our video scope is crossover problem in output images caused due to interpolation, which has to be rectified for more efficient performance.

• ETRI Journal
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• 제29권4호
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• pp.437-444
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• 2007

A CMOS frequency synthesizer block for multi-band orthogonal frequency division multiplexing ultra-wideband systems is proposed. The proposed frequency synthesizer adopts a double-conversion architecture for simplicity and to mitigate spur suppression requirements for out-of-band interferers in 2.4 and 5 GHz bands. Moreover, the frequency synthesizer can consist of the fewest nonlinear components, such as divide-by-Ns and a mixer with the proposed frequency plan, leading to the generation of less spurs. To evaluate the feasibility of the proposed idea, the frequency synthesizer block is implemented in 0.18-${\mu}m$ CMOS technology. The measured sideband suppression ratio is about 32 dBc, and the phase noise is -105 dBc/Hz at an offset of 1 MHz. The fabricated chip consumes 17.6 mA from a 1.8 V supply, and the die-area including pads is $0.9{\times}1.1\;mm^2$.

• Journal of Korea Society of Industrial Information Systems
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• 제17권3호
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• pp.27-34
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• 2012

This paper presents the impact of time dependent dielectric breakdown (TDDB, also called as gate oxide breakdown) failure on nanoscale digital CMOS Circuits. Recently, TDDB for ultra-thin gate oxides has been considered as one of the critical reliability issues which can lead to performance degradation or logic failures in nanoscale CMOS devices. Also, leakage power in the standby mode can be increased significantly. In this paper, TDDB aging effects on large CMOS digital circuits in the 45nm technology are analyzed. Simulation results show that TDDB effect on MOSFET circuits can result in more significant increase of power consumption compared to delay increase.

• Proceedings of the IEEK Conference
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• 대한전자공학회 1999년도 추계종합학술대회 논문집
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• pp.689-692
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• 1999

This paper describes a 10-bit 75-MHz CMOS current-mode DAC designed for 0.8${\mu}{\textrm}{m}$ double-poly double-metal CMOS technology. This D/A converter is implemented using a current cell matrix that can drive a resistive load without output buffer. In the DAC. a current source is proposed to reduce the linearity error caused by the threshold-voltage variations over a wafer and the glitch energy caused by the time lagging, The integral and differential linearity error are founded to be within $\pm$0.35 LSB and $\pm$0.31 LSB respectively. The maximum conversion rate is about 80 MS/s. The total power dissipation is 160 ㎽ at 75 MS/s conversion rate.

• JSTS:Journal of Semiconductor Technology and Science
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• 제6권4호
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• pp.270-274
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• 2006

A color filter array (CFA) helps a single electrical image sensor to recognize color images. The Red-Green-Blue (RGB) Bayer CFA is commonly used, but the amount of the light which arrives at the photodiode is attenuated with this CFA. Red-White-Blue (RWB) CFA increases the amount of the light which arrives at photodiode by using White (W) pixels instead of Green (G) pixels. However, white pixels are saturated earlier than red and blue pixels. The pseudo multiple capture scheme and the corresponding RWB CFA were proposed to overcome the early saturation problem of W pixels. The prototype CMOS image sensor (CIS) was fabricated with $0.35-{\mu}m$ CMOS process. The proposed CIS solves the early saturation problem of W pixels and increases the dynamic range.

• JSTS:Journal of Semiconductor Technology and Science
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• 제6권4호
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• pp.281-285
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• 2006

In order to widen the tuning range, capacitive degeneration is applied to fully CMOS LC VCOs. Small signal analysis shows that the fixed MOSFET capacitance seen by the LC tank is smaller than that of the traditional LC VCO, resulting in significant extension in the tuning range. This improvement in the tuning range has been verified through measurement of a 10-GHz LC VCO fabricated by $0.18{\mu}m$ CMOS process. The measured tuning range is from 9.8-GHz to 12-GHz, which is better than those of the reported CMOS LC VCOs in 10-GHz band. The measured phase noise is - 103dBc/Hz at 1MHz offset.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권6호
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• pp.873-879
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• 2016

A charge pump circuit with very short turn-on time is presented for minimizing reference spurs in CMOS PLL frequency synthesizers. In the source switching charge pump circuit, applying proper voltages to the source nodes of the current source FETs can significantly reduce the unwanted glitch at the output current while not degrading the rising time, thus resulting in low spur at the synthesizer output spectrum. A 1.1-1.6 GHz PLL synthesizer employing the proposed charge pump circuit is fabricated in 65 nm CMOS. The current consumption of the charge pump is $490{\mu}A$ from 1 V supply. Compared to the conventional charge pump, it is shown that the reference spur is improved by dB through minimizing the turn-on time. Theoretical analysis is described to show that the measured results agree well with the theory.

• Journal of IKEEE
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• 제7권1호
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• pp.1-8
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• 2003

In this study, the high performance BCD device structure which satisfies the high voltage and fast switching speed characteristics is devised. Through the process and device simulation, optimal process spec. & device spec. are designed. We adapt double buried layer structure, trench isolation process, n-/p-drift region formation and shallow junction technology to optimize an electrical property as mentioned above. This I.C consists of 20V level high voltage bipolar npn/pnp device, 60V level LDMOS device, a few Ampere level VDMOS, 20V level CMOS device and 5V level logic CMOS.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 한국전자파학회 2003년도 종합학술발표회 논문집 Vol.13 No.1
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• pp.113-117
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• 2003

This paper describes the design and the simulation results of the RF CMOS Class-E Power Amplifier for a 2.4GHz ISM band. This circuit is composed two connected amplifiers. where Class F amplifier drives Class E amplifier. The proposed circuit can reduce the total power dissipation of the driving stage and can work with higher efficiency. The power amplifier has been implemented in a standard $0.25{\mu}m$ CMOS technology and is shown to deliver 100mW output power to load with 41% power added efficiency(PAE) from a 2.5V supply.

• 한국정보통신설비학회:학술대회논문집
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• 한국정보통신설비학회 2006년도 하계학술대회
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• pp.205-207
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• 2006

In this paper, we present a design procedure of high linearity LNA using CMOS technology. To enhance the low linearity of the inherent CMOS transistor, we adopt the modified derivate superposition with adding external capacitor. The simulation of the designed LNA shows $IIP_3$ of +12-dBm, power gain of 13.8-dB, noise figure of 1.75-dB over the 900 MHz UHF RFID frequencies. The circuit draws the current of 4.2 mA from 1.8-V supply voltage.