• Transactions on Electrical and Electronic Materials
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• 제12권5호
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• pp.175-188
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• 2011

As complementary metal-oxide semiconductor (CMOS) continues to scale down deeper into the nanoscale, various device non-idealities cause the I-V characteristics to be substantially different from well-tempered metal-oxide semiconductor field-effect transistors (MOSFETs). The last few years witnessed a dramatic increase in nanotechnology research, especially the nanoelectronics. These technologies vary in their maturity. Carbon nanotubes (CNTs) are at the forefront of these new materials because of the unique mechanical and electronic properties. CNTFET is the most promising technology to extend or complement traditional silicon technology due to three reasons: first, the operation principle and the device structure are similar to CMOS devices and it is possible to reuse the established CMOS design infrastructure. Second, it is also possible to reuse CMOS fabrication process. And the most important reason is that CNTFET has the best experimentally demonstrated device current carrying ability to date. This paper discusses and reviewsthe feasibility of the CNTFET's application at this point of time in integrated circuits design by investigating different types of circuit blocks considering the advantages that the CNTFETs offer.

• 전자공학회논문지A
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• 제28A권10호
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• pp.821-829
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• 1991

In this paper, a BICMOS technology that has CMOS devices for digital application and bipolar devices for high voltage (80V) analog applications is presented. Basic concept to design BICMOS device is simple process technology without making too many performance trade-offs. The base line process is poly gate p-well CMOS process and three additional masking steps are added to improve bipolar characteristics. The key ingredients of bipolar integration are n+ buried layer process, up/down isolation process and p-well base process. The bipolar base region is formed simultaneously with the region of CMOS p-well area to reduce mask and heat cycle steps. As a result, hFE value of NPN bipolar transistor is 100-150(Ic=1mA). Collector resistance value is 138 ohm in case of bent type collector structure. Breakdown voltage of BVebo, BVcbo and BVceo are 21V, 115V and78V respectively. Threshold voltage is ${\pm}$1.0V for NMOS and PMOS transistor. Breakdown voltage of NMOS and PMOS transistor is obtained 22V and 19V respectively. 41 stage CMOS ring oscillator has 0.8ns delay time.

• JSTS:Journal of Semiconductor Technology and Science
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• 제2권1호
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• pp.30-40
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• 2002

A 2.45GHz double-balanced modified Gilbert-type CMOS up-conversion mixer design is introduced, where the PMOS current-reuse bleeding technique is demonstrated to be efficient in improving conversion gain, linearity, and noise performance. An LO buffer is included in the mixer design to perform single-ended to differential conversion of the LO signal on chip. Simulation results of the design based on careful modeling of all active and passive components are examined to explain in detail about the characteristic improvement and degradation provided by the proposed design. Two kinds of chips were fabricated using a standard $0.35\mu\textrm$ CMOS process, one of which is the mixer chip without the LO buffer and the other is the one with it. The measured characteristics of the fabricated chips are quite excellent in terms of conversion gain, linearity, and noise, and they are in close match to the simulation results, which demonstrates the adequacy of the modeling approach based on the macro models for all the active and passive devices used in the design. Above all the benefits provided by the current-reuse bleeding technique, the improvement in noise performance seems most valuable.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 추계학술대회 논문집
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• pp.347-348
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• 2007

On-chip micro humidity sensor, using $CN_x$ films for the sensing material, was designed, simulated, and fabricated with Op amp based readout circuit and diode temperature sensors. To compensate the temperature and other gases, two methods were applied. One is wheatstone-bridge with reference FET that eliminates other undesirable chemical species, and the other is a diode temperature sensor to compensate the temperature effect. $CN_x$ film can be a new humidity sensing material, and has a strong potential to adapt to smart sensors or multi-sensors using MEMS or nano-technology. A particular design technology for integration of sensors and systems together was proposed that whole fabrication process could be achieved by a standard CMOS process.

• 한국전기전자재료학회논문지
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• 제27권12호
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• pp.792-796
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• 2014

In this paper, we investigated the hot carrier reliability of two kinds of device with low threshold voltage (LVT) and regular threshold voltage (RVT) in 65 nm CMOS technology. Contrary to the previous report that devices beyond $0.18{\mu}m$ CMOS technology is dominated by channel hot carrier(CHC) stress rather than drain avalanche hot carrier(DAHC) stress, both of LVT and RVT devices showed that their degradation is dominated by DAHC stress. It is also shown that in case of LVT devices, contribution of interface trap generation to the device degradation is greater under DAHC stress than CHC stress, while there is little difference for RVT devices.

• 한국정보기술학회 영문논문지
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• 제10권1호
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• pp.37-43
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• 2020

This paper presents analysis of passive metal interconnection of the LNA block in CMOS integrated circuit. The performance of circuit is affected by the geometry of RF signal path. To investigate the effect of interconnection lines, a cascode LNA is designed, and circuit simulations with full-wave electromagnetic (EM) simulations are executed for different positions of a component. As the results, the position of an external capacitor (C_ex) changes the parasitic capacitance of electric coupling; the placement of component affects the circuit performance. This analysis of interconnection line is helpful to analyze the amount of electromagnetic coupling between the lines, and useful to choose the signal path in the layout design. The target of this work is the RF LNA enabling the seamless connection of wireless data network and the following standards have to be supported in multi-band (WCDMA: 2.11~ 2.17 GHz, CDMA200 1x : 1.84~1.87 GHz, WiBro : 2.3~2.4GHz) mobile application. This work has been simulated and verified by Cadence spectre RF tool and Ansoft HFSS. And also, this work has been implemented in a 0.13um RF CMOS technology process.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2004년도 ICCAS
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• pp.1561-1564
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• 2004

A CMOS-based Electronically Tunable Capacitance Multipliers, which can be magnified the value of a grounded unit capacitance, is presented in this article. The multiplication factor is varied by the ratio of the bias currents. The proposed circuit is simple, small in size and suitable for implementing in standard CMOS process. PSPICE simulation results demonstrating the characteristics of the proposed circuit are included.

• 센서학회지
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• 제18권1호
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• pp.95-101
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• 2009

A simple and new CMOS potentiostat circuit for amperometric sensor is described. To maintain a constant potential between the reference and working electrodes, only one differential difference amplifier (DDA) is needed in proposed design, while conventional potentiosatat requires at least 2 operational amplifiers and 2 resistors, or more than 3 operational amplifiers and 4 resistors for low voltage CMOS integrated potentiostat. The DDA with rail-to-rail design not only enables the full range operation to supply voltage but also provides simple potentiostat system with small hardwares and low power consumption.

• ETRI Journal
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• 제28권4호
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• pp.495-501
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• 2006

This paper presents a new CMOS fully-differential second-generation current conveyor (FDCCII). The proposed FDCCII is based on a fully-differential difference transconductor as an input stage and two class AB output stages. Besides the proposed FDCCII circuit operating at a supply voltage of ${\pm}1.5\;V$, it has a total standby current of $380\;{\mu}A$. The applications of the FDCCII to realize a variable gain amplifier, fully-differential integrator, and fully-differential second-order bandpass filter are given. The proposed FDCII and its applications are simulated using CMOS $0.35\;{\mu}m$ technology.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2008년도 하계종합학술대회
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• pp.531-532
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• 2008

In this paper, we present the comparison of the CMOS Double-Balanced Mixer for WLAN applications using the tail current source and not using it at the same current. The mixers are derived from the Gilbert cell mixer and have been simulated by using TSMC $0.18{\mu}m$ RF CMOS technology.