• Journal of electromagnetic engineering and science
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• v.18 no.1
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• pp.35-40
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• 2018

This study presents a vertical-type CMOS Hall device with improved sensitivity to detect a 3D magnetic field in various types of sensors or communication devices. To improve sensitivity, trenches are implanted next to the current input terminal, so that the Hall current becomes maximum. The effect of the dimension and location of trenches on sensitivity is simulated in the COMSOL simulator. A vertical-type Hall device with a width of $16{\mu}m$ and a height of $2{\mu}m$ is optimized for maximum sensitivity. The simulation result shows that it has a 23% better result than a conventional vertical-type CMOS Hall device without a trench.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.2
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• pp.246-251
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• 2014

In this paper, a high-speed CMOS Image Sensor (CIS) based on a 10-bit two step Single Slope A/D Converter (SS-ADC) is proposed. The A/D converter is composed of both 5-bit coarse ADC and a 6-bit fine ADC, and the conversion speed is 10 times faster than that of the single-slope A/D convertor. In order to reduce the pixel noise, further, a Hybrid Correlated Double Sampling (H-CDS) is also discussed. The proposed A/D converter has been fabricated with 0.13um 1-poly 4-metal CIS process, and it has a QVGA ($320{\times}240$) resolution. The fabricated chip size is $5mm{\times}3mm$, and the power consumption is about 35 mW at 3.3 V supply voltage. The measured conversion speed is 10 us, and the frame rate is 220 frames/s.

• Journal of Sensor Science and Technology
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• v.28 no.2
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• pp.71-75
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• 2019

This paper proposes the extension of the dynamic range in complementary metal oxide semiconductor (CMOS) image sensors (CIS) using switching operation of in-pixel inverter. A CMOS inverter is integrated in each unit pixel of the proposed CIS for switching operations. The n+/p-substrate photodiode junction capacitances are added to each unit pixel. When the output voltage of the photodiode is less than half of the power supply voltage of the CMOS inverter, the output voltage of the CMOS inverter changes from 0 V to the power supply voltage. Hence, the output voltage of the CMOS inverter is adjusted by changing the supply voltage of the CMOS inverter. Thus, the switching point is adjusted according to light intensity when the supply voltage of the CMOS inverter changes. Switching operations are then performed because the CMOS inverter is integrated with in each unit pixel. The proposed CIS is composed of a pixel array, multiplexers, shift registers, and biasing circuits. The size of the proposed pixel is $10{\mu}m{\times}10{\mu}m$. The number of pixels is $150(H){\times}220(V)$. The proposed CIS was fabricated using a $0.18{\mu}m$ 1-poly 6-metal CMOS standard process and its characteristics were experimentally analyzed.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.739-742
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• 2005

In this paper, an efficient detection algorithm for the flicker, which is caused by mismatching between light frequency and exposure time at CMOS image sensor (CIS), is proposed. The flicker detection can be implemented by specific hardware or complex signal processing logic. However it is difficult to implement on single chip image sensor, which has pixel, CDS, ADC, and ISP on a die, because of limited die area. Thus for the flicker detection, the simple algorithm and high accuracy should be achieved on single chip image sensor,. To satisfy these purposes, the proposed algorithm organizes only simple operation, which calculates the subtraction of horizontal luminance mean between continuous two frames. This algorithm was verified with MATLAB and Xilinx FPGA, and it is implemented with Magnachip 0.18 standard cell library. As a result, the accuracy is 95% in average on FPGA emulation and the consumed gate count is about 7,500 gates (@40MHz) for implementation using Magnachip 0.18 process.

• Journal of Sensor Science and Technology
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• v.19 no.4
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• pp.285-290
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• 2010

In this paper, a dynamic range(DR) extension technique based on a 3-transistor active pixel sensor(APS) and dual image sampling is proposed. The feature of the proposed APS is that the APS uses two or more photodiodes with different sensitivities, such as a high-sensitivity photodiode and a low-sensitivity photodiode. Compared with previously proposed wide DR(WDR) APS, the proposed approach has several advantages, such as no-external equipments or signal processing, no-additional time-requirement for additional charge accumulation, simple operation and adjustable DR extension by controlling parasitic capacitance and sensitivity of two photodiodes. Approximately 16 dB of DR extension was evaluated from the simulation for the situation of 10 times of sensitivity difference and the same size of parasitic capacitance between those two photodiodes.

• Journal of Sensor Science and Technology
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• v.22 no.4
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• pp.256-261
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• 2013

This paper presents an extension of the dynamic range in a complementary metal-oxide-semiconductor (CMOS) active pixel sensor (APS) using a stacked photodiode and feedback structure. The proposed APS is composed of two additional MOSFETs and stacked P+/N-well/P-sub photodiodes as compared with a conventional APS. Using the proposed technique, the sensor can improve the spectral response and dynamic range. The spectral response is improved using an additional stacked P+/N-well photodiode, and the dynamic range is increased using the feedback structure. Although the size of the pixel is slightly larger than that of a conventional three-transistor APS, control of the dynamic range is much easier than that of the conventional methods using the feedback structure. The simulation and measurement results for the proposed APS demonstrate a wide dynamic range feature. The maximum dynamic range of the proposed sensor is greater than 103 dB. The designed circuit is fabricated by the $0.35-{\mu}m$ 2-poly 4-metal standard CMOS process, and its characteristics are evaluated.

• Journal of Sensor Science and Technology
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• v.18 no.6
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• pp.475-484
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• 2009

In this paper, an analysis of the complementary CMOS active pixel and readout circuit is carried out. Complementary pixel structure which is different from conventional 3TR APS structure consists of photo diode, reset PMOS, several NMOSs and PMOSs sets for complementary signals. Proposed CMOS image sensors pixel has been fabricated using 0.5 standard CMOS process. Measured results show that the output signal range is from 0.8 V to 3.8 V. This output signal range increased 125 % compared to conventional 3TR pixel in the condition of 5 V power supply.

• Proceedings of the Korean Information Science Society Conference
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• 2007.10d
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• pp.255-260
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• 2007

무선통신과 하드웨어 기술의 발전에 의해 센서 네트워크에 사용되는 센서 노드의 성능은 점차 향상되어 가고 있다. 분만 아니라 최근에는 CMOS 이미지 센서 기술의 발전에 의해 센서 네트워크에 멀티미디어 데이터를 활용한 멀티미디어 센서 네트워크 연구가 활발히 진행 되고 있다. CMOS 이미지 센서는 기존의 CCD에 비해 저가격으로 생산이 가능하고 저전력의 특징을 가진다. 이러한 CMOS 이미지 센서를 활용한 멀티미디어 센서 네트워크는 기존의 센서 네트워크를 이용한 화재강시, 방법 시스템 등의 어플리케이션에 영상 데이터를 제공함으로써 보다 신뢰성있는 정보를 제공할 수 있다. 본 논문에서는 CMOS 이미지 센서를 이용한 이미지 센서 모듈과 이를 활용한 멀티미디어 센서네트워크를 설계 및 구현한다. 구현된 멀티미디어 센서 네트워크를 통해 이미지 데이터 수집을 테스트하고 그 성능을 분석한다.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.38 no.3
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• pp.31-39
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• 2001

In this paper, we proposed a new pixel circuit of the CMOS image sensor for high dynamic range operation, which is based on a multiple sampling scheme and a conditional reset circuit. To expand the pixel dynamic range, the output is multiple-sampled in the integration time. In each sampling, the pixel output is compared with a reference voltage, and the result of comparison may activate the conditional reset circuit. The times of conditional reset, N, during the integration will contribute to the increase of the dynamic range by the times of N. The test chip was fabricated with 0.65-${\mu}m$ CMOS technology (2-P, 2-M).

• Journal of the Korea Society of Computer and Information
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• v.6 no.1
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• pp.7-13
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• 2001

As the density of VLSI increases, the conventional logic testing is not sufficient to completely detect the new faults generated in design and fabrication processing. Recently. IDDQ testing becomes very attractive since it can overcome the limitations of logic testing. This paper presents a new BIC for the internal current test in CMOS logic circuit. Our circuit is composed of Magnetoresistive current sensor, level shifter, comparator, reference voltage circuit and a circuit be IDDQ tested as a kind of self-testing fashion by using the proposed BIC.