• 제어로봇시스템학회:학술대회논문집
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• 2000.10a
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• pp.514-514
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• 2000

In this article, the realization of a precision full-wave rectifier circuit for analog signal processing, which operates throughout in the current domain, is presented. The circuit makes use of a MOS class B/AB configuration, and provides a wide dynamic range and wide-band capability. The rectifier has a simple circuit configuration and is suitable for implementing in CMOS integrated circuit form as versatile building block. The characteristic of the circuit exhibits a low distortion en the output signal at low level input signal. PSPICE simulation results demonstrating the characteristic of the proposed circuit are included.

• IEIE Transactions on Smart Processing and Computing
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• v.3 no.6
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• pp.410-415
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• 2014

This paper presents a new rectifier with a bootstrapping technique to reduce the effective drop voltage. An all-digital delay locked loop (ADDLL) circuit was also applied to prevent the reverse leakage current. The proposed rectifier uses NMOS diode connected instead of PMOS to reduce the design size and improve the frequency respond. All the sub-circuits of ADDLL were designed with low power consumption to reduce the total power of the rectifier. The rectifier was implemented in CMOS $0.35{\mu}m$ technology. The peak power conversion efficiency was 76 % at an input frequency of 6.78MHz and a power level of 5W.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.28 no.6
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• pp.371-374
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• 2015

This paper suggests a high performance lateral super barrier rectifier (Lateral SBR) device which has the advantages of both Schottky diode and pn junction, that is, low forward voltage and low leakage current, respectively. Advantage of the proposed lateral SBR is that it can be easily implemented and integrated in current BCD platform. As a result of simulation using TCAD, BVdss = 48 V, $V_F=0.38V$ @ $I_F=35mA$, T_j = $150^{\circ}C$ were obtained with very low leakage current characteristic of 3.25 uA.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.3
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• pp.319-325
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• 2015

This paper presents an efficient vibration energy harvester with a piezoelectric (PE) cantilever. The proposed PE energy harvester increases the efficiency through minimization of hardware complexity and hence reduction of power dissipation of the circuit. Two key features of the proposed energy harvester are (i) incorporation synchronized switches with a simple control circuit, and (ii) a feed-forward buck converter with a simple control circuit. The chip was fabricated in $0.18{\mu}m$ CMOS processing technology, and the measured results indicate that the proposed rectifier achieves the efficiency of 77%. The core area of the chip is 0.2 mm2.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.11
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• pp.1091-1097
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• 2013

This paper presents a rectifier with comparator using unbalanced body biasing in $0.11{\mu}m$ RF CMOS process. It is composed of MOSFETs and two comparators. The comparator is used to reduce reverse leakage current which occurs when the load voltage is higher than input voltage. For the comparator, unbalanced body biasing is devised. By using unbalanced body biasing, reference voltage for comparator changing from high state to low state is increased, and it reduces time interval for leakage current to flow. 13.56 MHz 2 Vpp signal is used for input and $1k{\Omega}$ resistor and 1 nF capacitor are used for output load for simulation and experimental environment. In simulation environment, voltage conversion efficiency(VCE) is 87.5 % and Power conversion efficiency(PCE) is 50 %. When the rectifier is measured, VCE shows 90.203 % and PCE shows 45 %.

• Journal of Power Electronics
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• v.16 no.3
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• pp.1226-1235
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• 2016

For wearable health monitoring systems, a fundamental problem is the limited space for storing energy, which can be translated into a short operational life. In this paper, a highly efficient active voltage doubling rectifier with a wide input range for micro-piezoelectric energy harvesting systems is proposed. To obtain a higher output voltage, the Dickson charge pump topology is chosen in this design. By replacing the passive diodes with unbalanced-biased comparator-controlled active counterparts, the proposed rectifier minimizes the voltage losses along the conduction path and solves the reverse leakage problem caused by conventional comparator-controlled active diodes. To improve the rectifier input voltage sensitivity and decrease the minimum operational input voltage, two low power common-gate comparators are introduced in the proposed design. To keep the comparator from oscillating, a positive feedback loop formed by the capacitor C is added to it. Based on the SMIC 0.18-μm standard CMOS process, the proposed rectifier is simulated and implemented. The area of the whole chip is 0.91×0.97 mm², while the rectifier core occupies only 13% of this area. The measured results show that the proposed rectifier can operate properly with input amplitudes ranging from 0.2 to 1.0V and with frequencies ranging from 20 to 3000 Hz. The proposed rectifier can achieve a 92.5% power conversion efficiency (PCE) with input amplitudes equal to 0.6 V at 200 Hz. The voltage conversion efficiency (VCE) is around 93% for input amplitudes greater than 0.3 V and load resistances larger than 20kΩ.

• Journal of Electrical Engineering and Technology
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• v.13 no.6
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• pp.2441-2446
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• 2018

This paper presents a radio frequency-to-direct current (RF-to-DC) converter for special RF power harvesting application at 915 MHz. The major featured components of the proposed RF-to-DC converter is the combination of a cross-coupled rectifier and an active diode: first, the cross-coupled rectifier boosts the input voltage to desired level, and an active diode blocks the reverse current, respectively. A prototype was implemented using $0.18{\mu}m$ CMOS technology, and the performance was proven from the fact that the targeted RF harvesting system's full-operation with higher power efficiency; even if the system's input power gets lower (e.g., from nominal 0 to min. -12 dBm), the proposed RF-to-DC converter constantly provides 1.47 V, which is exactly the voltage level to drive follow up system components like DC-to-DC converter and so on. And, maximum power conversion efficiency is 82 % calculated from the 0 dBm input power, 2.3 mA load current.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.10a
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• pp.419-422
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• 2011

In this paper a dual-input self-powered power management system is proposed for low-power applications. The system is powered by merging the energy from a PZT vibration element and a solar cell. The proposed system consists of a charge pump for increasing the output voltage of a solar cell, a rectifier for DC conversion of the PZT output and a power management circuit for merging and managing the harvested energy. The performance of the design circuit has been verified through extensive simulation using a 0.18um CMOS technology. The chip area is $295um{\times}275um$.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.10
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• pp.881-886
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• 2003

This paper describes the design and implementation of a passive transponder chip for RFID applications. Passive transponders do not have their own power supply, and therefore all power required for the operation of a passive transponder must be drawn from the field of the reader. The designed transponder consists of a full wave rectifier to generate a dc supply voltage, a 128-bit mask ROM to store the information, and Manchester coding and load modulation circuits to be used for transmitting the information from the transponder to the reader. The transponder with a size 410 x 900 ${\mu}$m$^2$ has been fabricated using 0.65 ${\mu}$m 2-poly, 2-metal CMOS process. The measurement results show the data transmission rate of 3.9 kbps at RF frequency 125 kHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.3 s.357
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• pp.26-34
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• 2007

This Paper describes a chip design technique for body composition analyzer based on the BIA (Bioelectrical Impedance Analysis) method. All the functions of signal forcing circuits to the body, signal detecting circuits from the body, Micom, SRAM and EEPROMS are integrated in one chip. Especially, multi-frequency detecting method can be applied with selective band pass filter (BPF), which is designed in weak inversion region for low power consumption. In addition new full wave rectifier (FWR) is also proposed with differential difference amplifier (DDA) for high performance (small die area low power consumption, rail-to-rail output swing). The prototype chip is implemented with 0.35um CMOS technology and shows the power dissipation of 6 mW at the supply voltage of 3.3V. The die area of prototype chip is $5mm\times5mm$.