• Title/Summary/Keyword: CMOS fabrication process

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Fabrication, Mesurement and Evaluation of Silicon-Gate n-well CMOS Devices (실리콘 게이트 n-well CMOS 소자의 제작, 측정 및 평가)

  • Ryu, Jong-Seon;Kim, Gwang-Su;Kim, Bo-U
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.21 no.5
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    • pp.46-54
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    • 1984
  • A silicon-gate n-well CMOS process with 3 $\mu$m gate length was developed and its possibility for the applications was discussed,. Threshold voltage was easily controlled by ion implantation and 3-$\mu$m gate length with 650 $\AA$ oxide shows ignorable short channel effect. Large value of Al-n+ contact resistance is one of the problems in fabrications of VLSI circuits. Transfer characteristics of CMOS inverter is fairly good and the propagation delay time per stage in ring oscillator with layout of (W/L) PMOS /(W/L) NMOS =(10/5)/(5/5) is about 3.4 nsec. catch-up occurs on substrate current of 3-5 mA in this process and critically dependent on the well doping density and nt-source to n-well space. Therefore, research, more on latch-up characteristics as a function of n-well profile and design rule, especially n+-source to n-well space, is required.

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Impact of Plasma Induced Degradation on Low Temperature Poly-Si CMOS TFTs during Etching Process

  • Chang, Jiun-Jye;Chen, Chih-Chiang;Chuang, Ching-Sang;Yeh, Yung-Hui
    • 한국정보디스플레이학회:학술대회논문집
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    • 2002.08a
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    • pp.519-522
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    • 2002
  • In this paper, we analyze the impact of plasma etching process induced device degradation on low temperature poly-Si TFTs. The results indicate the relationship between device degradation and PPID effect during plasma fabrication. The dual-gate structure, which is used to suppress leakage current, is also discussed in this research.

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Thermo-piezoelectric $Si_3N_4$ cantilever array on a CMOS circuit for probe-based data storage using wafer-level transfer method (웨이퍼 본딩을 이용한 탐침형 정보 저장장치용 압전 켄틸레버 어레이)

  • Kim Young-Sik;Jang Seong-Soo;Lee Caroline Sun-Young;Jin Won-Hyeog;Cho Il-Joo;Nam Hyo-Jin;Bu Jong-Uk
    • Transactions of the Society of Information Storage Systems
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    • v.2 no.2
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    • pp.96-99
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    • 2006
  • In this research, a wafer-level transfer method of cantilever away on a conventional CMOS circuit has been developed for high density probe-based data storage. The transferred cantilevers were silicon nitride ($Si_3N_4$) cantilevers integrated with poly silicon heaters and piezoelectric sensors, called thermo-piezoelectric $Si_3N_4$ cantilevers. In this process, we did not use a SOI wafer but a conventional p-type wafer for the fabrication of the thermo-piezoelectric $Si_3N_4$ cantilever arrays. Furthermore, we have developed a very simple transfer process, requiring only one step of cantilever transfer process for the integration of the CMOS wafer and cantilevers. Using this process, we have fabricated a single thermo-piezoelectric $Si_3N_4$ cantilever, and recorded 65nm data bits on a PMMA film and confirmed a charge signal at 5nm of cantilever deflection. And we have successfully applied this method to transfer 34 by 34 thermo-piezoelectric $Si_3N_4$ cantilever arrays on a CMOS wafer. We obtained reading signals from one of the cantilevers.

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A 45GHz $f_{T}\;and\;50GHz\;f_{max}$ SiGe BiCMOS Technology Development for Wireless Communication ICs (무선통신소자제작을 위한 45GHz $f_{T}$ 및 50GHZz $f_{max}$ SiGe BiCMOS 개발)

  • Hwang Seok-Hee;Cho Dae-Hyung;Park Kang-Wook;Yi Sang-Don;Kim Nam-Ju
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.42 no.9 s.339
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    • pp.1-8
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    • 2005
  • A $0.35\mu$m SiGe BiCMOS fabrication process has been timely developed, which is aiming at wireless RF ICs development and fast growing SiGe RF market. With non-selective SiGe epilayer, SiGe HBTs in this process used trapezoidal Ge base profile for the enhanced AC performance via Ge induced bandgap niuoin. The characteristics of hFE 100, $f_{T}\;45GHz,\;F_{max}\;50GHz,\;NF_{min}\;0.8dB$ have been obtained by optimizing not only SiGe base profile but also RTA condition after emitter polysilicon deposition, which enables the SiGe technology competition against the worldwide cutting edge SiGe BiCMOS technology. In addition, the process incorporates the CMOS logic, which is fully compatible with $0.35\mu$m pure logic technology. High Q passive elements are also provided for high precision analog circuit designs, and their quality factors of W(1pF) and inductor(2nH) are 80, 12.5, respectively.

Integrated Circuit Design Based on Carbon Nanotube Field Effect Transistor

  • Kim, Yong-Bin
    • Transactions on Electrical and Electronic Materials
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    • v.12 no.5
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    • pp.175-188
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    • 2011
  • As complementary metal-oxide semiconductor (CMOS) continues to scale down deeper into the nanoscale, various device non-idealities cause the I-V characteristics to be substantially different from well-tempered metal-oxide semiconductor field-effect transistors (MOSFETs). The last few years witnessed a dramatic increase in nanotechnology research, especially the nanoelectronics. These technologies vary in their maturity. Carbon nanotubes (CNTs) are at the forefront of these new materials because of the unique mechanical and electronic properties. CNTFET is the most promising technology to extend or complement traditional silicon technology due to three reasons: first, the operation principle and the device structure are similar to CMOS devices and it is possible to reuse the established CMOS design infrastructure. Second, it is also possible to reuse CMOS fabrication process. And the most important reason is that CNTFET has the best experimentally demonstrated device current carrying ability to date. This paper discusses and reviewsthe feasibility of the CNTFET's application at this point of time in integrated circuits design by investigating different types of circuit blocks considering the advantages that the CNTFETs offer.

Giga-bps CMOS Clock and Data Recovery Circuit with a novel Adaptive Phase Detector (새로운 구조의 적응형 위상 검출기를 갖는 Gbps급 CMOS 클럭/데이타 복원 회로)

  • 이재욱;이천오;최우영
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.27 no.10C
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    • pp.987-992
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    • 2002
  • In this paper, a new clock and data recovery circuit is proposed for the application of data communication systems requiring ㎓-range clock signals. The circuit is suitable for recovering NRZ data which is widely used for high speed data transmission in ㎓ ranges. The high frequency jitter is one of major performance-limiting factors in PLL, particularly when NRZ data patterns are used. A novel phase detector is able to suppress this noise, and stable clock generation is achieved. Futhermore, the phase detector has an adaptive delay cell removing the dead zone problem and has the optimal characteristics for fast locking. The proposed circuit has a convenience structure that can be easily extended to multi-channels. The circuit is designed based on CMOS 0.25㎛ fabrication process and verified by measurement result.

Fabrication and Electrical Properties of Highly Organized Single-Walled Carbon Nanotube Networks for Electronic Device Applications

  • Kim, Young Lae
    • Journal of the Korean Ceramic Society
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    • v.54 no.1
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    • pp.66-69
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    • 2017
  • In this study, the fabrication and electrical properties of aligned single-walled carbon nanotube (SWCNT) networks using a template-based fluidic assembly process are presented. This complementary metal-oxide-semiconductor (CMOS)-friendly process allows the formation of highly aligned lateral nanotube networks on $SiO_2/Si$ substrates, which can be easily integrated onto existing Si-based structures. To measure outstanding electrical properties of organized SWCNT devices, interfacial contact resistance between organized SWCNT devices and Ti/Au electrodes needs to be improved since conventional lithographic cleaning procedures are insufficient for the complete removal of lithographic residues in SWCNT network devices. Using optimized purification steps and controlled developing time, the interfacial contact resistance between SWCNTs and contact electrodes of Ti/Au is reached below 2% of the overall resistance in two-probe SWCNT platform. This structure can withstand current densities ${\sim}10^7A{\cdot}cm^{-2}$, equivalent to copper at similar dimensions. Also failure current density improves with decreasing network width.

Effects of DI Rinse and Oxide HF Wet Etch Processes on Silicon Substrate During Photolithography (반도체 노광 공정의 DI 세정과 Oxide의 HF 식각 과정이 실리콘 표면에 미치는 영향)

  • Baik, Jeong-Heon;Choi, Sun-Gyu;Park, Hyung-Ho
    • Korean Journal of Materials Research
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    • v.20 no.8
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    • pp.423-428
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    • 2010
  • This study shows the effects of deionized (DI) rinse and oxide HF wet etch processes on silicon substrate during a photolithography process. We found a fail at the wafer center after DI rinse step, called Si pits, during the fabrication of a complementary metal-oxide-semiconductor (CMOS) device. We tried to find out the mechanism of the Si pits by using the silicon wafer on CMOS fabrication and analyzing the effects of the friction charge induced by the DI rinsing. The key parameters of this experiment were revolution per minute (rpm) and time. An incubation time of above 10 sec was observed for the formation of Si pits and the rinsing time was more effective than rpm on the formation of the Si pits. The formation mechanism of the Si pits and optimized rinsing process parameters were investigated by measuring the charging level using a plasma density monitor. The DI rinse could affect the oxide substrate by a friction charging phenomenon on the photolithography process. Si pits were found to be formed on the micro structural defective site on the Si substrate under acceleration by developed and accumulated charges during DI rinsing. The optimum process conditions of DI rinse time and rpm could be established through a systematic study of various rinsing conditions.

The Design and Fabrication of Reduced Phase Noise CMOS VCO (위상 잡음을 개선한 CMOS VCO의 설계 및 제작)

  • Kim, Jong-Sung;Lee, Han-Young
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.18 no.5 s.120
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    • pp.539-546
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    • 2007
  • In this paper, a 3-D EM simulation methodology for on-chip spiral inductor analysis has provided and it is shown that the methodology can be adapted to the highly predictable design for CMOS VCO. LC-resonator type VCO have fabricated by using standard 0.25 um CMOS process. And the LC VCO layout case which has pattern ground shielded inductors and the other layout case which has no pattern grounded inductors were fabricated for the verification of their effects on the VCO's phase noise by reducing the Q-factor of inductors. Fabricated VCO has 3.094 GHz, -12.15 dBm output at the tuning voltage of 2.5 V, and from the simulation, Q-factor of the pattern grounded inductor has increased 8% at 3 GHz, and from the measurement results, the phase noise has reduced by 9 dB at the 3 MHz off-set frequency for the pattern grounded inductor layout case.

A Study on Implanted and Annealed Antimony Profiles in Amorphous and Single Crystalline Silicon Using 10~50 keV Energy Bombardment (비정질 및 단결정 실리콘에서 10~50 keV 에너지로 주입된 안티몬 이온의 분포와 열적인 거동에 따른 연구)

  • Jung, Won-Chae
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.28 no.11
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    • pp.683-689
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    • 2015
  • For the formation of $N^+$ doping, the antimony ions are mainly used for the fabrication of a BJT (bipolar junction transistor), CMOS (complementary metal oxide semiconductor), FET (field effect transistor) and BiCMOS (bipolar and complementary metal oxide semiconductor) process integration. Antimony is a heavy element and has relatively a low diffusion coefficient in silicon. Therefore, antimony is preferred as a candidate of ultra shallow junction for n type doping instead of arsenic implantation. Three-dimensional (3D) profiles of antimony are also compared one another from different tilt angles and incident energies under same dimensional conditions. The diffusion effect of antimony showed ORD (oxygen retarded diffusion) after thermal oxidation process. The interfacial effect of a $SiO_2/Si$ is influenced antimony diffusion and showed segregation effects during the oxidation process. The surface sputtering effect of antimony must be considered due to its heavy mass in the case of low energy and high dose conditions. The range of antimony implanted in amorphous and crystalline silicon are compared each other and its data and profiles also showed and explained after thermal annealing under inert $N_2$ gas and dry oxidation.