• Journal of the Institute of Convergence Signal Processing
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• v.6 no.3
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• pp.134-142
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• 2005

The implementation of Multiple-Valued Logic(MVL) based on Current-Mode CMOS Logic(CMCL) circuits has recently been achieved. In this paper, four-valued Unary Multiple-Valued logic functions are synthesized using current-mode CMOS logic circuits. We properly make use of the fact that the CMCL addition of logic values represented using discrete current values can be performed at no cost and that negative logic values are readily available via reversing the direction of current flow. A synthesis process for CMCL circuits is based upon a logically complete set of basic elements. Proposed algorithm results in less expensive realization than those achieved using existing techniques in terms of the number of transistors needed. As an alternative to the cost-table techniques Universal Unary Programmable Circuit (UUPC) for a unary function is also proposed.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.10
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• pp.33-37
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• 2007

This paper presents the implementation technique to reduce circuit area occupation in designing Low Noise Amplifier (LNA) using vertical shunt symmetric inductor. We applied a vertical shunt symmetric inductor to match the input and output in 3 GHz CMOS LNA to reduce the circuit area. This size efficient amplifier has been designed in a $0.18\;{\mu}m$ digital logic CMOS process. In this paper, the case of conventional asymmetric inductor, and vertical shunt symmetrical inductor with a relatively higher number of turns have been compared in order to efficient a size efficient CMOS LNA design method while still retaining the circuit operation characteristics.

• Journal of the Korea Society of Computer and Information
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• v.6 no.1
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• pp.7-13
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• 2001

As the density of VLSI increases, the conventional logic testing is not sufficient to completely detect the new faults generated in design and fabrication processing. Recently. IDDQ testing becomes very attractive since it can overcome the limitations of logic testing. This paper presents a new BIC for the internal current test in CMOS logic circuit. Our circuit is composed of Magnetoresistive current sensor, level shifter, comparator, reference voltage circuit and a circuit be IDDQ tested as a kind of self-testing fashion by using the proposed BIC.

• Journal of Sensor Science and Technology
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• v.14 no.1
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• pp.28-32
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• 2005

In this paper, a CMOS integrated detection circuit for capacitive type fingerprint sensor signal processing is described. We designed a detection circuit of charge-sharing sensing scheme. The proposed detection circuit increases the voltage difference between a ridge and valley. The test chip is composed of $160{\times}192$ array sensing cells (12 by $12.7{\;}mm^{2}$). The chip was fabricated on a 0.35 m standard CMOS process. Measured difference voltage between a ridge and valley was 0.95 V.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.89-92
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• 2001

In this paper, a simple low-power CMOS current reference circuit is proposed. The reference circuit includes parasitic pnp BJTs and resistors. Temperature compensation is made by adding a current component proportional to a thermal voltage to a current component proportional to a base-to-emitter voltage. The designed circuit has been simulated using a 0.25${\mu}{\textrm}{m}$ n-well CMOS process parameters. The simulation results show that the reference current is 34.96$mutextrm{A}$$\pm$0.04$mutextrm{A}$ in the temperature range of -2$0^{\circ}C$ to 12$0^{\circ}C$ The reference current varies less than 0.6% when the power supply voltage changes from 2.5V to 3.5V For $V_{DD=5V}$ and T=3$0^{\circ}C$ the power consumption is 520㎼ during normal operation but reduces to 0.l㎻ during power-down mode.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.7
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• pp.11-19
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• 1998

A signal line potential variation due to the delta-I noise was physically investigated in CMOS integrated circuits. An equivalent circuit for the noise analysis was presented. The signal line was modeled as segmented RC-lumped circuits with the ground noise. Then the equivalent circuit was mathematically analyzed. Therebvy a new signal line potential variation model due to the switching mosie was developed. Th emodel was verified with 0.35.mu.m CMOS deivce model parameters. The model has an excellent agreement with HSPICE simulation. Thus the proposed model can be dirctly employed in the industry to design the high-performance integrted circuit design as well as integrated circuit package design.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.6
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• pp.873-879
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• 2016

A charge pump circuit with very short turn-on time is presented for minimizing reference spurs in CMOS PLL frequency synthesizers. In the source switching charge pump circuit, applying proper voltages to the source nodes of the current source FETs can significantly reduce the unwanted glitch at the output current while not degrading the rising time, thus resulting in low spur at the synthesizer output spectrum. A 1.1-1.6 GHz PLL synthesizer employing the proposed charge pump circuit is fabricated in 65 nm CMOS. The current consumption of the charge pump is $490{\mu}A$ from 1 V supply. Compared to the conventional charge pump, it is shown that the reference spur is improved by dB through minimizing the turn-on time. Theoretical analysis is described to show that the measured results agree well with the theory.

• Journal of Sensor Science and Technology
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• v.18 no.4
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• pp.280-285
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• 2009

In this paper, we designed a 2-stage CMOS operational amplifier with temperature compensation function using 2-poly 4-metal 0.35 $\mu$m standard CMOS technology. Using two bias circuits, the positive temperature coefficient(PTC) and the negative temperature coefficient(NTC) of the bias circuit are canceled out each other. When reference current circuit is simulated that it has a temperature coefficient of -150 ppm/$^{\circ}C$ with a temperature change from 0 $^{\circ}C$ to 120 $^{\circ}C$. Also the proposed circuit has a temperature coefficient of -0.011 dB/$^{\circ}C$ of DC open loop gain with the same temperature range.

• Proceedings of the KIEE Conference
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• 1988.07a
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• pp.574-578
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• 1988

This paper proposes testable design method of Domino CMOS NOR-NOR Array Logic design method. Previous Domino CMOS PLA method is composed of 2 level NAND-NAND Logic. Because NOR-NOR Logic is realized by a parallel circuit, this method can prevent delay time each level and DNOR-PLA include testable circuit system that DNOR-PLA circuit. DNOR-PLA testable algorithm is realized on Prime (Primos) in Pascal language and DNOR-PLA circuit is simulated by PSPICE.

• Journal of Korea Society of Industrial Information Systems
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• v.6 no.3
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• pp.123-127
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• 2001

The prediction method of the parameter C/sub gs/ of CMOS transistor is proposed by calculating the mobil charge in inversion layer of COMS transistor. This parameter C/sub gs/ decided on the cutoff frequency in MOS transistor in RF range and coupled input and output. This parameter C/sub gs/ in RF range is very important parameter in small signal circuit model. This proposed method is contributed to developing software of extracting parameter value in equivalent circuit model. The method provide the important information to construct a RF nonlinear model for multifinger gate MOSFET. This method will be very valuable to develop a large signal MOSFET model for nonlinear RF IC design.