• ETRI Journal
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• v.31 no.4
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• pp.478-480
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• 2009

The design of a CMOS clamped-clamped beam resonator along with a full custom integrated differential amplifier, monolithically fabricated with a commercial 0.35 ${\mu}m$ CMOS technology, is presented. The implemented amplifier, which minimizes the negative effect of the parasitic capacitance, enhances the electrical MEMS characterization, obtaining a $48{\times}10^8$ resonant frequency-quality factor product ($Q{\times}f_{res}$) in air conditions, which is quite competitive in comparison with existing CMOS-MEMS resonators.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.2
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• pp.280-285
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• 2015

A fully integrated high-efficiency linear CMOS power amplifier (PA) is developed for 802.11n WLAN applications using the 65-nm standard CMOS technology. The transformer topology is investigated to obtain a high-efficiency and high-linearity performance. By adopting a 2:2 output transformer, an optimum impedance is provided to the PA core. Besides, a LC harmonic control block is added to reduce the AM-to-AM/AM-to-PM distortions. The CMOS PA produces a saturated power of 26.1 dBm with a peak power-added efficiency (PAE) of 38.2%. The PA is tested using an 802.11n signal, and it satisfies the stringent error vector magnitude (EVM) and mask requirements. It achieves -28-dB EVM at an output power of 18.6 dBm with a PAE of 14.7%.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.28 no.10
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• pp.832-835
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• 2017

In this paper, V-band differential low noise amplifier(LNA) using 65-nm CMOS process for high speed wireless data communication is presented. The LNA is composed of 3-stage common-source differential amplifiers with neutralization of feedback capacitances using MOS capacitors and impedance matching utilizing transformers. The fabricated LNA has a peak gain of 23 dB at 63 GHz and 3 dB bandwidth of 6 GHz. The chip area of LNA is $0.3mm^2$ and the LNA consumes 32 mW DC power from 1.2 V supply voltage.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.11
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• pp.83-91
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• 1990

VOC(coltage controlled oscillator) circuits are necessary in applications such at the demodul-ation of FM signals, frequency synthesizer, and for clock recovery from digital data. In this paper, we designed the VCO circuit based on a OTA(operational transconductance amplifier) and the OP amp which using a differential amplifier by BiCMOS circuit. It consists of a OTA, voltage contorolled integrator and a schmitt trigger. Conventional VCO circuits are designed using the CMOS circuit, but in this paper we designed newly BiCMOS VCO circuit which has a good drive avlity, As a result of SPICE simulation, output frequency is 141KHz at 105KHz, and sensitivity is 15KHz.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.10a
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• pp.423-424
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• 2011

This paper has proposed a 920 MHz RF front-end for IEEE 802.15.4g SUN (Smart Utility Network) systems. The proposed 920 MHz RF front-end consists of a driver amplifier, a low noise amplifier, and a RF switch. In the TX mode, the driver amplifier has been designed as a single-ended topology to remove a transformer which causes a loss of the output power from the driver amplifier. In addition, a RF switch is located in the RX path not the TX path. In the RX mode, the proposed low noise amplifier can provide a differential output signal when a single-ended input signal has been applied to. A LC resonant circuit is used as both a load of the drive amplifier and a input matching circuit of the low noise amplifier, reducing the chip area. The proposed 920 MHz RF Front-end has been implemented in a 0.18-um CMOS technology. It consumes 3.6 mA in driver amplifier and 3.1 mA in low noise amplifier from a 1.8 V supply voltage.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.43 no.11 s.353
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• pp.175-184
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• 2006

In this paper, we describe a 900MHz CMOS RF transceiver using an ISM band for ZigBee applications. The architecture of the designed rx front-end, which consists of a low noise amplifier, a down-mixer, a programmable gain amplifier and a band pass filter. And the tx front-end, which consists of a band pass filter, a programmable gain amplifier, an up-mixer and a drive amplifier. A low-if topology is adapted for transceiver architecture, and the total current consumption is reduced by using a low power topology. Entire transceiver is verified by means of post-layout simulation and is implemented in 0.18um RF CMOS technology. The fabricated chip demonstrate the measured results of -92dBm minimum rx input level and 0dBm maximum tx output level. Entire power consumption is 32mW(@1.8VDD). Die area is $2.3mm{\times}2.5mm$ including ESD protection diode pads.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.10
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• pp.31-39
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• 2009

This paper presents the single supply power line communication(PLC) SoC ASIC with built-in analog frond-end circuit. To achieve the low power consumption along with low chip cost, this PLC SoC ASIC employs fully CMOS analog front-end(AFE) and several built-in Regulators(LDOs) powering for Core logic, ADC, DAC and IP Pad driver. The AFE includes RX of pre-amplifier, Programmable gain amplifier and 10 bit ADC and TX of 10bit Digital Analog Converter and Line driver. This PLC Soc was implemented with 0.18um 1 Poly 5 Metal CMOS process. The single power supply of 3.3V is required for the internal LDOs. The total power consumption is below 30mA at standby and 300mA at active which meets the eco-design requirement. The chips size is $3.686\;{\times}\;2.633\;mm^2$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.6
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• pp.48-51
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• 2009

One-stage low noise amplifier (LNA) using 65 nm RF CMOS technology below 20 GHz is designed to find the optimal bias voltage and optimal width of input transistor so that the maximum figure of merit (FoM) has been achieved. If the frequency is higher than 13 GHz, the amplifier needs two-stage to achieve the higher gain. If the frequency is lower than 5 GHz, one additional capacitor between gate and source should be added to control the power under the limitation. This paper summarizes one-stage LNA overall performances below 20 GHz and this approach can also be applied to other CMOS technology of LNA designs.

• Journal of electromagnetic engineering and science
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• v.5 no.3
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• pp.112-116
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• 2005

This paper presents a broadband two-stage low noise amplifier(LNA) operating from 3 to 10 GHz, designed with 0.18 ${\mu}m$ RF CMOS technology, The cascode feedback topology and broadband matching technique are used to achieve broadband performance and input/output matching characteristics. The proposed UWB LNA results in the low noise figure(NF) of 3.4 dB, input/output return loss($S_{11}/S_{22}$) of lower than -10 dB, and power gain of 14.5 dB with gain flatness of $\pm$1 -dB within the required bandwidth. The input-referred third-order intercept point($IIP_3$) and the input-referred 1-dB compression point($P_{ldB}$) are -7 dBm and -17 dBm, respectively.

• ETRI Journal
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• v.29 no.2
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• pp.212-218
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• 2007

A novel low-voltage CMOS current feedback operational amplifier (CFOA) is presented. This realization nearly allows rail-to-rail input/output operations. Also, it provides high driving current capabilities. The CFOA operates at supply voltages of ${\pm}0.75V$ with a total standby current of 304 ${\mu}A$. The circuit exhibits a bandwidth better than 120 MHz and a current drive capability of ${\pm}1$ mA. An application of the CFOA to realize a new all-pass filter is given. PSpice simulation results using 0.25 ${\mu}m$ CMOS technology parameters for the proposed CFOA and its application are given.