• The Magazine of the IEIE
• /
• v.29 no.9
• /
• pp.18-30
• /
• 2002

Wireless communication systems will be one of the biggest drivers of semiconductor products over the next decade. Global Positioning System (GPS) and Blue-tooth, HomeRF, and Wireless-LNA system are just a few of RF-module candidate awaiting integration into next generation mobile phone. Motivated by the generation mobile phone. Motivated by the growing needs for low-cost and multi-band/multi-function single chip wireless transceivers, CMOS technology has been recognized as a most promising candidate for the implementation of the future wireless communication systems. This paper presents recent developments in RF CMOS technology, which is classified into device technology and circuit technology and from them forecasts technology and from them forecasts technology trends in the near future.

• Electronics and Telecommunications Trends
• /
• v.10 no.1 s.35
• /
• pp.1-17
• /
• 1995

본 연구에서는 아날로그 CMOS IC 제조를 위한 CMOS 소자기술 및 수동소자 기술인, 다결정실리콘 저항과 다결정실리콘(I)/산화막/다결정실리콘(II) 구조를 가진 커패시터의 공정기술을 개발하였다. 아날로그 CMOS 공정기술은 디지털 CMOS 공정에서 다결정실리콘 저항과 커패시터 공정이 추가됨으로씨 발생할 수 있는 CMOS 소자특성의 변화를 최소화하는 데 중점을 두어 개발하였다. 최종적으로 개발된 $1.2\mum$ 아날로그 CMOS 공정을 이용하여 10 비트 ADC 및 DACIC를 제작한 후 정상적인 동작을 확인함으로써, $1.2\mum$ 아날로그 CMOS 공정에 의한 아날로그 IC 제작의 응용 가능성을 검증하였다. 개발된 $1.2\mum$ 아날로그 CMOS 공정은 향후 $0.8\mum$ 아날로그 CMOS IC 개발에 크게 기여할 것으로 기대된다.

• Journal of the Korean Institute of Telematics and Electronics B
• /
• v.30B no.11
• /
• pp.1-10
• /
• 1993

This paper proposes a High Performance Full-Swing BiCMOS (HiF-BiCMOS) circuit which improves on the conventional BiCMOS circuit. The HiF-BiCMOS circuit has all the merits of the conventional BiCMOS circuit and can realize full-swing logic operation. Especially, the speed of full-swing logic operation is much faster than that of conventional full-swing BiCMOS circuit. And the number of transistors added in the HiF-BiCMOS for full-swing logic operation is constant regardless of the number of logic gate inputs. The HiF-BiCMOS circui has high stability to variation of environment factors such as temperature. Also, it has a preamorphized Si layer was changed into the perfect crystal Si after the RTA. Remarkable scalability for power supply voltage according to the development of VLSI technology. The power dissipation of HiF-BiCMOS is very small and hardly increases about a large fanout. Though the Spice simulation, the validity of the proposed circuit design is proved.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.14 no.4
• /
• pp.383-390
• /
• 2014

This paper presents an excitatory CMOS neuron oscillator circuit design, which can synchronize two neuron-bursting patterns. The excitatory CMOS neuron oscillator is composed of CMOS neurons and CMOS excitatory synapses. And the neurons and synapses are connected into a close loop. The CMOS neuron is based on the Hindmarsh-Rose (HR) neuron model and excitatory synapse is based on the chemical synapse model. In order to fabricate using a 0.18 um CMOS standard process technology with 1.8V compatible transistors, both time and amplitude scaling of HR neuron model is adopted. This full-chip integration minimizes the power consumption and circuit size, which is ideal for motion control unit of the proposed bio-mimetic micro-robot. The experimental results demonstrate that the proposed excitatory CMOS neuron oscillator performs the expected waveforms with scaled time and amplitude. The active silicon area of the fabricated chip is $1.1mm^2$ including I/O pads.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2000.04b
• /
• pp.180-183
• /
• 2000

Beginning with a brief introduction on near 100 nm or below CMOS devices, this paper addresses novel devices for future sub-100 nm CMOS. First, key issues such as gate materials, gate dielectric, source/drain, and channel in Si bulk CMOS devices are considered. CMOS devices with different channel doping and structure are introduced by explaining a figure of merit. Finally, novel device structures such as SOI, SiGe, and double-gate devices will be discussed for possible candidates for sub-100 nm CMOS.

• The Magazine of the IEIE
• /
• v.29 no.9
• /
• pp.1020-1020
• /
• 2002

Wireless communication systems will be one of the biggest drivers of semiconductor products over the next decade. Global Positioning System (GPS) and Blue-tooth, HomeRF, and Wireless-LNA system are just a few of RF-module candidate awaiting integration into next generation mobile phone. Motivated by the growing needs for low-cost and multi-band/multi-function single chip wireless transceivers, CMOS technology has been recognized as a most promising candidate for the implementation of the future wireless communication systems. This paper presents recent developments in RF CMOS technology, which is classified into device technology and circuit technology and from them forecasts technology trends in the near future.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.42 no.9 s.339
• /
• pp.1-8
• /
• 2005

A $0.35\mu$m SiGe BiCMOS fabrication process has been timely developed, which is aiming at wireless RF ICs development and fast growing SiGe RF market. With non-selective SiGe epilayer, SiGe HBTs in this process used trapezoidal Ge base profile for the enhanced AC performance via Ge induced bandgap niuoin. The characteristics of hFE 100, $f_{T}\;45GHz,\;F_{max}\;50GHz,\;NF_{min}\;0.8dB$ have been obtained by optimizing not only SiGe base profile but also RTA condition after emitter polysilicon deposition, which enables the SiGe technology competition against the worldwide cutting edge SiGe BiCMOS technology. In addition, the process incorporates the CMOS logic, which is fully compatible with $0.35\mu$m pure logic technology. High Q passive elements are also provided for high precision analog circuit designs, and their quality factors of W(1pF) and inductor(2nH) are 80, 12.5, respectively.

• Journal of information and communication convergence engineering
• /
• v.13 no.3
• /
• pp.180-188
• /
• 2015

As a potential alternative to the complementary metal-oxide semiconductor (CMOS) technology, many researchers are focusing on carbon-nanotube field-effect transistors (CNFETs) for future electronics. However, existing studies report the advantages of CNFETs over CMOS at the device level by using small-scale circuits, or over outdated CMOS technology. In this paper, we propose a methodology of analyzing CNFET-based circuits and study its impact at the full-chip scale. First, we design CNFET standard cells and use them to construct large-scale designs. Second, we perform parasitic extraction of CNFET devices and characterize their timing and power behaviors. Then, we perform a full-chip analysis and show the benefits of CNFET over CMOS in 45-nm and 20-nm designs. Our full-chip study shows that in the 45-nm design, CNFET circuits achieve a 5.91×/3.87× (delay/power) benefit over CMOS circuits at a density of 200 CNTs/µm. In the 20-nm design, CNFET achieves a 6.44×/3.01× (delay/power) benefit over CMOS at a density of 200 CNTs/µm.

• 제어로봇시스템학회:학술대회논문집
• /
• 2003.10a
• /
• pp.948-950
• /
• 2003

In this literature, the CMOS current mode fout quadrant differentiator circuit is proposed. The implementation is base on an appropriate input stage that converts the input current into a compressed voltage at the input capacitor ($C_{gs}$) of the CMOS driver circuit. This input voltage use as the control output current which flow to the output node by passing through a MOS active load and use it as the feedback voltage to the input node. Simulation results with level 49 CMOS model of MOSIS are given to demonstrate the correct operation of the proposed configuration. But the gain of the circuit is too low so the output differentiate current also low. The proposed differentiator is expected to find several applications in analog signal processing system.

• 제어로봇시스템학회:학술대회논문집
• /
• 2003.10a
• /
• pp.970-973
• /
• 2003

Abstract An idea to redce the direct-path short circuit current of the CMOS digital integrated circuit is present. The sample circuit model of the CMOS digital circuit is the CMOS current-control digital output driver circuit, which are also suitable for the low voltage supply integrated circuits as the simple digital inverter, are present in this title. The circuit consists of active MOS load as the current control source, which construct from the saturated n-channel and p-channel MOSFET and the general CMOS inverter circuits. The saturated MOSFET bias can control the output current and the frequency response of the circuit. The experimental results show that lower short circuit current control can make the lower frequency response of the circuit.