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http://dx.doi.org/10.6109/jicce.2015.13.3.180

Full-Chip Power/Performance Benefits of Carbon Nanotube-Based Circuits  

Song, Taigon (School of Electrical and Computer Engineering, Georgia Institute of Technology)
Lim, Sung Kyu (School of Electrical and Computer Engineering, Georgia Institute of Technology)
Publication Information
Journal of information and communication convergence engineering / v.13, no.3, 2015 , pp. 180-188 More about this Journal
Abstract
As a potential alternative to the complementary metal-oxide semiconductor (CMOS) technology, many researchers are focusing on carbon-nanotube field-effect transistors (CNFETs) for future electronics. However, existing studies report the advantages of CNFETs over CMOS at the device level by using small-scale circuits, or over outdated CMOS technology. In this paper, we propose a methodology of analyzing CNFET-based circuits and study its impact at the full-chip scale. First, we design CNFET standard cells and use them to construct large-scale designs. Second, we perform parasitic extraction of CNFET devices and characterize their timing and power behaviors. Then, we perform a full-chip analysis and show the benefits of CNFET over CMOS in 45-nm and 20-nm designs. Our full-chip study shows that in the 45-nm design, CNFET circuits achieve a 5.91×/3.87× (delay/power) benefit over CMOS circuits at a density of 200 CNTs/µm. In the 20-nm design, CNFET achieves a 6.44×/3.01× (delay/power) benefit over CMOS at a density of 200 CNTs/µm.
Keywords
Carbon nanotube FET; Circuits; Full-chip; VLSI;
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