• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.2
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• pp.138-143
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• 2003

A double spiral thin-film inductor with a NiFe magnetic core is integrated with DC-DC converter IC. The NiFe core is deposited on a polyimide film as the thinckness of NiFe is 2.5~3.5 ${\mu}$m. Then, copper conductor line is deposited on the NiFe core with double spiral structure. Process integration is performed by sequential processes of etching the polyimide film deposited both top and bottom of the NiFe core and electroplation copper conductor line from exposed metal pad of the DC-DC converter IC. Process integration is simplified by elimination planarization process for top core because the proposed thin-film inductor has a bottom NiFe core only. Inductor of the fabricated monolithic DC-DC converter IC is 0.53 ${\mu}$H when the area of converter IC and thin-film inductor are 5X5$\textrm{mm}^2$ and 3.5X2.5$\textrm{mm}^2$, respectively. The efficiency is 72% when input voltage and output voltage are 3.5 V and 6 V, respectively at the operation frequency of 8 MHz.

• Proceedings of the Materials Research Society of Korea Conference
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• 1996.05a
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• pp.64-64
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• 1996

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.2
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• pp.63-71
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• 2002

This paper suggests a 8-bit RISC microcontroller, which has a 4-stage pipeline architecture. Many low-power design techniques that have been proposed by previous works are adopted into it. The proposed microcontroller consumes only 600㎼ per MIPS for 0.6 ${\mu}{\textrm}{m}$ CMOS process and even lower power of 70㎼ per MIPS for 0.25${\mu}{\textrm}{m}$ process. The RTL level design of this microcontroller is carried out using VHDL. The functional verification is thoroughly done at the gate level using 0.6${\mu}{\textrm}{m}$/0.25${\mu}{\textrm}{m}$ CMOS IDEC standard cell library. This microcontroller contains 7000 NAND gates on a 0.36$\textrm{mm}^2$ die using 0.25${\mu}{\textrm}{m}$ process. Finally the comparison of power consumption with other conventional microcontrollers is provided.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.5B
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• pp.974-984
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• 2000

A CMOS voltage driver circuit for voltage down converter is proposed. An adaptive biasing technique is used to enhance load regulation characteristics. The proposed driver circuit uses the NMOS transistor as a driving transistor, so it does not suffer from large Miller capacitances which is one of the problems with conventional PMOS driving transistor, and hence achieves good phase margin and stable frequency response. No additional complex circuit for frequency compensation such as compensation capacitor is required in this implementation. For the same current capability, the size of NMOS transistor in driver circuit is smaller than that of PMOS counterpart. So the smaller die area can be achieved. The circuits is implemented using a 0.8 ${\mu}{\textrm}{m}$ CMOS process and has a die area of 150 ${\mu}{\textrm}{m}$ x 360 ${\mu}{\textrm}{m}$. Proposed circuit has a quiescent power of 60 . In the current driving range from 100 $mutextrm{A}$ to 50 ㎃, load regulation of 5.6 ㎷ is measured.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.8
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• pp.41-46
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• 2012

A quadrature voltage controlled oscillator(QVCO) for X-band is presented in this paper. The QVCO has fabricated in Charted $0.13{\mu}m$ CMOS process. The QVCO consists of two cross-coupled differential VCO and two differential buffers. The QVCO is controlled by 4 bit of capacitor bank and control voltage of varactor. To have a linear quality factor of varactors, voltage biases of varactors are difference. The QVCO generates frequency tuning range from 6.591 GHz to 8.012 GHz. The phase noise is -101.04 dBc/Hz at 1MHz Offset when output frequency is 7.150 GHz. The supply voltage is 1.5 V and core current 6.5-8.5 mA.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.8
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• pp.61-70
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• 2009

A 10b 30MS/s pipelined ADC operating under 1V power supply is presented. It utilizes a switched-RC based input sampling circuit and a resistive loop to reset the feedback capacitor in the multiplying digital-to-analog converter (MDAC) for the low-voltage operation. Cascaded switched-RC branches are used to achieve accurate grain of the MDAC for the first stage and separate switched-RC circuits are used in the sub-ADC to suppress the switching noise coupling to the MDAC input The measured differential and integral non-linearities of the prototype ADC fabricated in a 0.13${\mu}m$, CMOS process are less than 0.54LSB and 1.75LSB, respectively. The prototype ADC achieves 54.1dB SNDR and 70.4dB SFDR with 1V supply and 30MHz sampling frequency while consuming 17mW power.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.11
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• pp.89-94
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• 2007

For successful implementation of multi-standard transmitter, reconfigurable architecture and component design are essential. This paper presents a reconfigurable CMOS power amplifier designed CMOS 0.25 um process. Designed power amplifier can be operated at 0.9, 1.2, 1.75, and 1.85 GHz. Also, it can be used at 2.4 GHz by using bonding wire inductor. The interstage matching network is composed of two inductors and four switches, and operation frequency can be varied by controlling switches. Proposed power amplifier can be used as a power amplifier in low power applications such as ZigBee or Bluetooth application and used as a driver amplifier in high power application such as CDMA application. Designed power amplifier has 18.2 dB gain and 10.3 dBm output power at 0.9 GHz. Also, it represented 10.3 (18.1) dB gain and 5.2 (10) dBm output power at 1.75 (2.4) GHz.

• Journal of IKEEE
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• v.20 no.2
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• pp.192-195
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• 2016

In this paper, we present a nanopower CMOS bandgap voltage reference working in sub-threshold region without resisters and bipolar junction transistors (BJT). Complimentary to absolute temperature (CTAT) voltage generator was realized by using two n-MOSFET pair with body bias circuit to make a sufficient amount of CTAT voltage. Proportional to absolute temperature (PTAT) voltage was generated from differential amplifier by using different aspect ratio of input MOSFET pair. The proposed circuits eliminate the use of resisters and BJTs for the operation in a sub-1V low supply voltage and for small die area. The circuits are implemented in 0.18um standard CMOS process. The simulation results show that the proposed sub-BGR generates a reference voltage of 290mV, obtaining temperature coefficient of 92 ppm/$^{\circ}C$ in -20 to $120^{\circ}C$ temperature range. The circuits consume 15.7nW at 0.63V supply.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.27 no.3
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• pp.330-333
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• 2016

In this paper, we propose 77 GHz power amplifier for long range automotive collision avoidance radar using 65 nm CMOS process. The proposed circuit has a 3-stage single power amplifier which includes common source structure and transformer. The measurement results show 18.7 dB maximum voltage gain at 13 GHz 3 dB bandwidth. The measured maximum output power is 10.2 dBm, input $P_{1dB}$ is -12 dBm, output $P_{1dB}$ is 5.7 dBm, and maximum power add efficiency is 7.2 %. The power amplifier consumes 140.4 mW DC power from 1.2 V supply voltage.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.4
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• pp.36-42
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• 2008

40Gb/s CMOS Clock and Data Recovery circuit design for optical serial link is proposed. The circuit generates 8 multiphase clock using LC tank PLL and controls the phase between the clock and the data using the $2{\times}$ oversampling Bang-Bang PD. 40Gb/s input data is 1:4 demultiplexed and recovered to 4 channel 10Gb/s outputs. The design was progressed to separate the analog power and the digital power. The area of the chip is $2.8{\times}2.4mm^2$ for the inductors and the power dissipation is about 200mW. The chip has been fabricated using 0.18um CMOS process. The measured results show that the chip recovers the data up to 9.5Gb/s per channel(Equivalent to serial input rate of up to 38Gb/s).