• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.6
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• pp.35-42
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• 2010

This paper describes a 10 bit 80MHz CMOS D/A converter for wireless communication system. The proposed circuit in the paper is implemented with a $0.18{\mu}m$ CMOS n-well 1-poly 6-metal process. The architecture of the circuit consists of the 4bit LSB with binary decoder, and both the 3bit ULSB and the 3bit MSB with the thermometer decoder. The measurement results demonstrates SFDR of 60.42dBc at sampling frequency 80MHz, input frequency 1MHz and ENOB of 8.75bit. INL and DNL have been measured to be ${\pm}$0.38LSB and ${\pm}$0.32LSB and glitch energy is measured to be 4.6$pV{\cdot}s$. Total power dissipation is 48mW at 80MHz(maximum sampling frequency) with a single power supply of 1.8V.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.11
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• pp.13-20
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• 2008

In this paper, an 1.8V 12-bit 10MSPS CMOS A/D converter (ADC) is described. The architecture of the proposed ADC is based on a folding and interpolation using an even folding technique. For the purpose of improving SNR, cascaded-folding cascaded-interpolation technique, distributed track and hold are adapted. Further, a digital encoder algorithm is proposed for efficient digital process. The chip has been fabricated with $0.18{\mu}m$ 1-poly 4-metal n-well CMOS technology. The effective chip area is $2000{\mu}m{\times}1100{\mu}m$ and it consumes about 250mW at 1.8V power supply. The measured SNDR is about 46dB at 10MHz sampling frequency.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.4
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• pp.137-145
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• 2008

In this paper, novel CMOS charge pump having NMOS and PMOS transfer switches and a bulk-pumping circuit has been proposed. The NMOS and PMOS transfer switches allow the charge pump to improve the current-driving capability at the output. The bulk-pumping circuit effectively solves the bulk forward problem of the charge pump. To verify the effectiveness, the proposed charge pump was designed using a 80-nm CMOS process. The comparison results indicate that the proposed charge pump enhances the current-driving capability by more than 47% with pumping speed improved by 9%, as compared to conventional charge pumps having either NMOS or PMOS transfer switch. They also indicate that the charge pump reduces the worst-case forward bias of p-type bulk by more than 24%, effectively solving the forward current problem.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.4
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• pp.86-93
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• 2008

A low-power, low-noise, highly-linear hybrid balun circuit is proposed for 2.4-GHz fully differential CMOS direct conversion receivers. The hybrid balun is composed of a passive transformer and loss-compensating auxiliary amplifiers. Design issues regarding the optimal signal splitting and coupling between the transformer and compensating amplifiers are discussed. Implemented in $0.18{\mu}m$ CMOS process, the 2.4 GHz hybrid balun achieves 2.8 dB higher gain and 1.9 dB lower noise figure than its passive counterpart and +23 dBm of IIP3 only at a current consumption of 0.67 mA from 1.2 V supply. It is also examined that the hybrid balun can remarkably lower the total noise figure of a 2.4 GHz fully differential RF receiver only at a cost of 0.82 mW additional power dissipation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.39A no.12
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• pp.691-698
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• 2014

An L-band single side band(SSB) mixer with CMOS switches and a C-band quadrature voltage-controlled oscillator(QVCO) have been developed using the TowerJazz 0.18-um RFCMOS process. The SSB mixer exhibits a conversion gain of 6.6 ~ 7.5 dB with a 70-dBc image rejection ratio and 65-dBc port isolation. The oscillation frequency range of the QVCO is 6.2 ~ 6.7 GHz with an output power of 4~6 dBm. For measurement, 1.8 V supply voltage is used while drawing 36 mA for the mixer and 23 mA for the QVCO.

• Journal of Sensor Science and Technology
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• v.23 no.5
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• pp.332-336
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• 2014

In this paper, we propose a complementary metal oxide semiconductor (CMOS) binary image sensor with a gate/body-tied (GBT) PMOSFET-type photodetector for high-speed operation. The GBT photodetector of an active pixel sensor (APS) consists of a floating gate ($n^+$-polysilicon) tied to the body (n-well) of the PMOSFET. The p-n junction photodiode that is used in a conventional APS has a good dynamic range but low photosensitivity. On the other hand, a high-gain GBT photodetector has a high level of photosensitivity but a narrow dynamic range. In addition, the pixel size of the GBT photodetector APS is less than that of the conventional photodiode APS because of its use of a PMOSFET-type photodetector, enabling increased image resolution. A CMOS binary image sensor can be designed with simple circuits, as a complex analog to digital converter (ADC) is not required for binary processing. Because of this feature, the binary image sensor has low power consumption and high speed, with the ability to switch back and forth between a binary mode and an analog mode. The proposed CMOS binary image sensor was simulated and designed using a standard CMOS $0.18{\mu}m$ process.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.3
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• pp.211-219
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• 2001

This paper describes a read-only CMOS transponder IC for RFID applications. A full-wave rectifier implemented using NMOS transistors supplies the transponder with a dc supply voltage using the magnetic field generated from a reader. A 64-bit ROM has been designed for a data memory. Front-end impedance modulation and Manchester coding are used for transmitting the data from the transponder memory to the reader. A new damping circuit which has almost constant damping rate under the variations of the distance between the transponder and the reader has been employed for impedance modulation. The designed circuit has been fabricated using a 0.65${\mu}{\textrm}{m}$2-poly, 2-metal CMOS process. Die area is 0.9mm$\times$0.4mm. Measurement results show that it has a constant damping rate of around 20~25% and a data transmission rate of 3.9kbps at a 125KHz RF carrier. The power required for reading operation is about 100㎼. The measured reading distance is around 7cm.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.5
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• pp.48-55
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• 1999

This paper describes automatic gain control circuit (AGC) design techniques for CMOS CCD camera interface systems. The required gain of the AGC in the proposed system is controlled directly by digital bits without conventional extra D/A converters and the signal settling behavior is almost independent of AGC gain variation at video speeds. A capacitor-segment combination technique to obtain large capacitance values considerably improves the effective bandwidth of the AGC based on switched-capacitor techniques. A proposed layout scheme for capacitor implementation shows AGC matching accuracy better than 0.1 %. The outputs from the AGC are transferred to a 10b A/D converter integrated on the same chip. The proposed AGC is implemented as a sub-block of a CCD camera interface system using a 0.5 um n-well CMOS process. The prototype shows the 32-dB AGC dynamic range in 1/8-dB steps with 173 mW at 3 V and 25 MHz.

• The Journal of the Korea institute of electronic communication sciences
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• v.15 no.3
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• pp.479-486
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• 2020

In this paper, we present a design method for improving the linearity and dynamic range of the analog current mode multiplier circuit, which is one of the key devices in an analog current mode AI processor. The proposed circuit consists of 4 quadrant translinear loops made up of NMOS transistors only, which minimizes physical mismatches of the transistors. The proposed circuit can be implemented at 117㎛ × 109㎛ in 0.35㎛ CMOS process and has a total harmonic distortion of 0.3%. The proposed analog current mode multiplier is expected to be useful as the core circuit of a current mode AI processor.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.3
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• pp.397-409
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• 1993

This paper proposed the design methodology of the 8 bit binary parallel adder with carry book-ahead scheme via current-mode CMOS multivalued logic and simulated the proposed adder under $5{\mu}m$ standard IC process technology. The threshold conditions of $G_K$ and $P_K$ which are needed for m-valued parallel adder with CLA are evaluated and adopted for quaternary logic. The design of quaternary CMOS logic circuits, encoder, decoder, mod-4 adder, $G_K$ and $P_K$ detecting circuit and current-voltage converter is proposed and is simulated to prove the operations. These circuits are necessary for binary arithmetic using multivalued logic. By comparing with the conventional binary adder and the CCD-MVL adder, We show that the proposed adder cab be designed one look-ahead carry generator with 1-level structure under standard CMOS technology and confirm the usefulness of the proposed adder.