• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.353-356
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• 1999

A 3.3V PLL(Phase Locked loop) is designed for a high frequency, low voltage, and low power applications. This paper proposes a new PLL architecture to improve voltage to frequency linearity of VCO(Voltage controlled oscillator) with new delay cell. The proposed VCO operates at a wide frequency range of 30MHz~1㎓ with a good linearity. The DC-DC voltage up/down converter is utilized to regulate the control voltage of the two-stage VCO. The designed PLL architecture is implemented on a 0.6${\mu}{\textrm}{m}$ n-well CMOS process. The simulation results show a locking time of 2.6$\mu$sec at 1Hz, Lock in range of 100MHz~1㎓, and a power dissipation of 112㎽.

• ETRI Journal
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• v.23 no.2
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• pp.77-84
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• 2001

The detection of open defects in CMOS SRAM has been a time consuming process. This paper proposes a new dynamic power supply current testing method to detect open defects in CMOS SRAM cells. By monitoring a dynamic current pulse during a transition write operation or a read operation, open defects can be detected. In order to measure the dynamic power supply current pulse, a current monitoring circuit with low hardware overhead is developed. Using the sensor, the new testing method does not require any additional test sequence. The results show that the new test method is very efficient compared with other testing methods. Therefore, the new testing method is very attractive.

• Proceedings of the IEEK Conference
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• 2000.06e
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• pp.191-194
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• 2000

A 2.4 GHz single ended two stage low noise amplifier(LNA) is designed for Bluetooth application. The circuit was implemented in a standard digital 0.25 $\mu\textrm{m}$ CMOS process with one poly and five metal layers. At 2.4 GHz, the LNA dissipates 34.5 mW from a 2.5V power supply voltage and provides 24.6 dB power gain, 2.85 dB minimum noise figure, -66.3 dB reverse isolation, and an output 1-dB compression level of 8.5 dBm.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.6
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• pp.754-759
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• 2016

A transformer feedback low-noise amplifier (LNA) is implemented in a standard $0.18{\mu}m$ CMOS process, which exploits drain-to-gate transformer feedback technique for wideband input matching and operates across entire 3~5 GHz ultra-wideband (UWB). The proposed LNA achieves power gain above 9.5 dB, input return loss less than 15.0 dB, and noise figure below 4.8 dB, while consuming 8.1 mW from a 1.8-V supply. To the authors' knowledge, drain-to-gate transformer feedback for wideband input matching cascode LNA is the first adopted technique for UWB application.

• Proceedings of the KIEE Conference
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• 1997.11a
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• pp.339-341
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• 1997

From this first studies, We have investigated the latch-up characteristics of various CMOS well structures possible with high energy ion implantation processes. In this study, we also investigated those of STI(Shallow Trench Isolation} structures with varing n+/p+ spacing and the depth of trench. STI structure is formed by T-SUPREM4 process simulator, and then latch-up simulations for each case were performed by MEDICI device simulator for latch-up immunity improvement. STI is very effective to preventing the degradation of latch-up characteristics as the n+/p+ spacing is reduced. These studies will allow us to evaluate each technology and suggest guidelines for the optimization of latch-up susceptibility.

• Journal of Sensor Science and Technology
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• v.20 no.1
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• pp.14-18
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• 2011

An analytical pinning-voltage model of a pinned photodiode has been proposed and derived. The pinning-voltage is calculated using doping profiles based on shallow- and exponential-junction approximations. Therefore, the derived pinning-voltage model is analytically expressed in terms of the process parameters of the implantation. Good agreement between the proposed model and simulated results has been obtained. Consequently, the proposed model can be used to predict the pinning-voltage and related performance of a pinned photodiode in a CMOS active pixel sensor.

• Proceedings of the KIEE Conference
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• 1988.07a
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• pp.533-536
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• 1988

For CMOS, this paper propose a new global routing algorithm in which macrocells and I/O padcells can be treated. Not only predefined feedthrough in base array, but also some polysilicon line which are not assigned as inputs are used to prevent the overflow of nets passing through the row. The signal nets are assigned on their feedthrough by the maze router. By treating macrocells and I/O padcell, the routing from internal to I/O cell can be done automatically and a kind of is constraints in design process can be reduced.

• Electrical & Electronic Materials
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• v.5 no.3
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• pp.320-327
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• 1992

Twin-tub CMOS 공정에 의해 제작된 서브마이크로미터 채널길이를 갖는 n채널 및 p채널 MOSFET의 특성을 고찰하였다. n채널 및 p채널 영역에서의 불순물 프로파일과 채널 이온주입 조건에 따른 문턱전압의 의존성 및 퍼텐셜 분포를 SUPREM-II와 MINIMOS 4.0을 사용하여 시뮬레이션하였다. 문턱전압 조정을 위한 counter-doped 보론 이온주입에 의해 p채널 MOSFET는 표면에서 대략 0.15.mu.m의 깊이에서 매몰채널이 형성되었다. 각 소자의 측정 결과, 3.3[V] 구동을 위한 충분한 여유를 갖는 양호한 드레인 포화 특성과 0.2[V]이하의 문턱전압 shift를 갖는 최소화된 짧은 채널 효과, 10[V]이상의 높은 펀치쓰루 전압과 브레이크다운 전압, 낮은 subthreshold 값을 얻었다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.21 no.4
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• pp.311-320
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• 2008

In this paper, a 2.4 GHz low-voltage CMOS double-balanced down-conversion mixer using neutralization technique has been proposed and verified by circuit simulations and measurements. The grounded source structure was used for low-voltage operation. The neutralization technique was used to improve a conversion gain. The proposed mixer is fabricated in $0.25{\mu}m$ CMOS process for a 2.4 GHz wireless receiver. The mixer consumes 1.94 mW and gives conversion gain of 5.66 dB, input IP3 of 0.7 dBm and P1dB of -11.2 dBm at 1.5 V power supply. Measured results for the designed mixer show improved conversion gain of 2.86 dB over conventional mixer of grounded source structure.

• ETRI Journal
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• v.33 no.3
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• pp.462-465
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• 2011

A millimeter-wave (mm-wave) high-linear low-noise amplifier (LNA) is presented using a 0.18 ${\mu}m$ standard CMOS process. To improve the linearity of mm-wave LNAs, we adopted the multiple-gate transistor (MGTR) topology used in the low frequency range. By using an MGTR having a different gate-source bias at the last stage of LNAs, third-order input intercept point (IIP3) and 1-dB gain compression point ($P_{1dB}$) increase by 4.85 dBm and 4 dBm, respectively, without noise figure (NF) degradation. At 33 GHz, the proposed LNAs represent 9.5 dB gain, 7.13 dB NF, and 6.25 dBm IIP3.