• The Transactions of the Korean Institute of Electrical Engineers C
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• v.49 no.1
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• pp.1-7
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• 2000

The SNOSFET memory devices with ultrathin ONO(tunnel oxide-nitride-blocking oxide) gate dielectric were fabricated using n-well CMOS process and investigated its characteristics. The thicknesses of tunnel oxide, nitride and blocking oxide were $23{\AA},\; 53{\AA}\; and\; 33{\AA}$, respectively. Auger analysis shows that the ONO layer is made up of $SiO_2(upper layer of blocking oxide)/O-rich\; SiO_x\N\_y$. It clearly shows that the converting layer with $SiO_x\N\_y(lower layer of blocking oxide)/N-rich SiO_x\N\_y(nitride)/O-rich SiO_x\N\_y(tunnel oxide)$. It clearly shows that the converting layer with $SiO_x\N\_y$ phase exists near the interface between the blocking oxide and nitride. The programming condition of +8 V, 20 ms, -8 V, 50 ms is determined and data retention over 10 years is obtained. Under the condition of 8 V programming, it was confirmed that the modified Fowler-Nordheim tunneling id dominant charge transport mechanism. The programmed threshold voltage is distributed less than 0.1 V so that the reading error of memory stated can be minimized. An $8\times8$ NAND type flash EEPROM with SONOSFET memory cell was designed and simulated with the extracted SPICE parameters. The sufficient read cell current was obtained and the upper limit of $V_{TH}$ for write state was over 2V.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.3 s.357
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• pp.52-58
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• 2007

This paper describes the PLL of TCON(Timing Controller) chip for FPD(Flat Panel Display). The recent TCON requires wide range frequency operation of $8\sim135MHz$ in PLL. In order to be satisfied this requirement the new V-I converter.circuit. The V-I converter of new architecture increased the minimum/maximum current ratio which widens the operation frequency range of VCO's md also guaranteed linearity of VCO's. The proposed PLL circuits in FPD TCON show the measuring performance of loops RMS jitter in the range of $8\sim135MHz$. The designed circuit was fabricated in 1-ploy 3-metal 0.25um TSMC process technology and has a operation range or $8\sim135MHz$ with 2.5V power.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.8
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• pp.24-31
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• 2008

Power converters are becoming an essential block in modem mobile multimedia application. This paper presents a high performance DC-DC buck converter for mobile applications. Controller of DC-DC buck converter is designed by current-mode control method. An current-mode DC-DC converter is implemented in a standard $0.18{\mu}m$ CMOS process, and the overall die size was $1.2mm^2$. The peak efficiency was 86 % with a switching frequency of $1\sim1.5MHz$ and a maximum load current of 400mA.

• Journal of IKEEE
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• v.11 no.1 s.20
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• pp.54-60
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• 2007

In this study novel ESD protection device, namely, N/P-type Low Voltage Triggered SCR, has been proposed, for high speed I/O interface. Proposed device could lower high trigger voltage($\sim$20V) of conventional SCR and reduce latch-up phenomenon of protection device during the normal condition. In this Study, the proposed NPLVTSCR has been simulated using TMA MEDICI device simulator for electrical characteristic. Also the proposed device's test pattern was fabricated using 90nm TSMC's CMOS process and was measured electrical characteristic and robustness. In the result, NPLVTSCR has 3.2V $\sim$ 7.5V trigger voltage and 2.3V $\sim$ 3.2V holding voltage by changing PMOS gate length and it has about 2kV, 7.5A HBM ESD robustness(IEC61000-4-2).

• The Bulletin of The Korean Astronomical Society
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• v.39 no.2
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• pp.91.1-91.1
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• 2014

IGRINS (the Immersion GRating INfrared Spectrometer) is a high resolution wide-band infrared spectrograph developed by the Korea Astronomy and Space Science Institute (KASI) and the University of Texas at Austin (UT). This spectrograph has H-band and K-band science cameras, both of which use Teledyne's $2.5{\mu}m$ cutoff $2k{\times}2k$ HgCdTe HAWAII-2RG CMOS science grade detectors. Teledyne's cryogenic SIDECAR ASIC boards and JADE2 USB interface cards were installed to control these detectors. We performed lab experiments and test observations to optimize and evaluate the detector systems of science cameras. In this presentation, we describe a process to optimize bias voltages and way to reduce pattern noise with reference pixel subtraction schemes. We also present measurements of the following properties under optimized settings of bias voltages at cryogenic temperature (70K): read noise, Fowler noise, dark current, and reference-level stability, full well depth, linearity and conversion gain.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.39 no.4
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• pp.25-35
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• 2002

This work describes an 8b 200MHz time-interleaved subranging analog-to-digital converter (ADC) based on a single-poly digital CMOS process. Two fine ADCs for lower digital bits of the proposed ADC employ a time-sharing double-channel architecture to increase system speed and a new reference voltage switching scheme to reduce settling time of the reference voltages and chip area. The proposed intermeshed resistor string, which generates reference voltages for fine ADCs, improves linearity and settling time of the reference voltages simultaneously. The proposed sample- and-hold amplifier(SHA) is based on a highly linear common-drain amplifier and passive differential circuits to minimize power consumption and chip area with 8b accuracy and employs input dynamic common mode feedback circuits for high dynamic performance at a 200MHz sampling rate. A new encoding circuit in a coarse ADC simplifies the signal processing between the coarse ADC and two successive fine ADCs.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.3
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• pp.311-320
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• 2008

In this paper, a new variable active inductor using a conventional grounded active inductor with feedback variable LC-resonator is proposed. The grounded active inductor is realized by the gyrator-C topology and the variable LC-resonator is realized by the low-Q spiral inductor and varactor. This variable LC-resonator can compensate the degradation of Q-factor due to parasitic capacitance of a transistor, and the frequency range with high Q-factor is adjustable by resonance frequency adjustment of LC-resonator. The fabricated variable active inductor with Magnachip $0.18{\mu}m$ CMOS process shows that high-Q frequency range can be adjusted according to varactor control voltage from 4.66 GHz to 5.45 GHz and Q-factor is higher than 50 in the operating frequency ranges. The measured inductance at 4.9GHz can be controlled from 4.12 nH to 5.97 nH by control voltage.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.4
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• pp.31-43
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• 1999

The main goal of this paper is to design a high performance SVP(Stack based Video Processor) for network applications. The SVP is a comprehensive scheme; 'better' in the sense that it is an optimal selection of previously proposed enhancements of a stack machine and a video processor. This can process effectively object-based video data using a S-RISC(Stack-based Reduced Instruction Set Computer) with a semi -general-purpose architecture having a stack buffer for OOP(Object-Oriented Programming) with many small procedures at running programs. And it includes a vector processor that can improve the MPEG coding speed. The vector processor in the SVP can execute advanced mode motion compensation, motion prediction by half pixel and SA-DCT(Shape Adaptive-Discrete Cosine Transform) of MPEG-4. Absolutors and halfers in the vector processor make this architecture extensive to a encoder. We also designed a VLSI stack-oriented video processor using the proposed architecture of stack-oriented video decoding. It was designed with O.5$\mu\textrm{m}$ 3LM standard-cell technology, and has 110K logic gates and 12 Kbits SRAM internal buffer. The operating frequency is 50MHz. This executes algorithms of video decoding for QCIF 15fps(frame per second), maximum rate of VLBV(Very Low Bitrate Video) in MPEG-4.

• IEMEK Journal of Embedded Systems and Applications
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• v.11 no.2
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• pp.97-105
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• 2016

Microcontrollers (MCUs) for endpoint smart sensor devices of internet-of-thing (IoT) are being implemented as system-on-chip (SoC) with on-chip instruction flash memory, in which user firmware is embedded. MCUs directly fetch binary code-based instructions through bit-line sense amplifier (S/A) integrated with on-chip flash memory. The S/A compares bit cell current with reference current to identify which data are programmed. The S/A in reading '0' (erased) cell data consumes a large sink current, which is greater than off-current for '1' (programmed) cell data. The main motivation of our approach is to reduce the number of accesses of erased cells by binary code level transformation. This paper proposes a built-in write/read path architecture using binary code inversion method based on hot-spot region detection of instruction code access to reduce sensing current in S/A. From the profiling result of instruction access patterns, hot-spot region of an original compiled binary code is conditionally inverted with the proposed bit-inversion techniques. The de-inversion hardware only consumes small logic current instead of analog sink current in S/A and it is integrated with the conventional S/A to restore original binary instructions. The proposed techniques are applied to the fully-custom designed MCU with ARM Cortex-M0$^{TM}$ using 0.18um Magnachip Flash-embedded CMOS process and the benefits in terms of power consumption reduction are evaluated for Dhrystone$^{TM}$ benchmark. The profiling environment of instruction code executions is implemented by extending commercial ARM KEIL$^{TM}$ MDK (MCU Development Kit) with our custom-designed access analyzer.

• The Journal of the Korea institute of electronic communication sciences
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• v.11 no.7
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• pp.665-670
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• 2016

In this paper, we suggest the design of OP-AMP using MOSFET in the operation of sub-threshold condition as a basic unit of an IoT. The sub-threshold operation of MOSFET is useful for an ultra low power consumption of sensor network system in the IoT, because it cause the supply voltage to be reduced. From the simulation result using 0.35 um CMOS process, the supply voltage, VDD can be reduced with 0.6 V, open-loop gain of 43 dB and the power consumption was evaluated with about $1.3{\mu}W$ and the active size for an integration was measured with $64{\mu}m{\times}105{\mu}m$. It is expected that the proposed circuit is applied to the low power sensor network for IoT.