• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.1
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• pp.112-117
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• 2016

This paper presents a half-rate current-integrating DFE receiver with sub-unit interval (sub-UI) inter-symbol interference (ISI) cancellation. By having a single additional DFE tap in each data path, the proposed DFE receiver can minimize BER degradation due to input pattern dependency and feedback tap latency problems in conventional current-integrating DFE receivers. The proposed DFE receiver was designed and fabricated in a 45 nm CMOS process, whose measurement results indicated that the BER bathtub width is increased from 0.235 UI to 0.315 UI (34% improvement) at $10^{-12}$ BER level.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.1
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• pp.31-38
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• 2016

A novel self-reference sense amplifier with parallel reading during writing operation is proposed. Read access time is improved compared to conventional self-reference scheme with fast operation speed by reducing operation steps to 1 for read operation cycle using parallel reading scheme, while large sense margin competitive to conventional destructive scheme is obtained by using self-reference scheme. The simulation was performed using standard $0.18{\mu}m$ CMOS process. The proposed self-reference sense amplifier improved not only the operation speed of less than 20 ns which is comparable to non-destructive sense amplifier, but also sense margin over 150 mV which is larger than conventional sensing schemes. The proposed scheme is expected to be very helpful for engineers for developing MRAM technology.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.1
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• pp.23-30
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• 2016

We report a STT-MRAM write-scheme, in which the length of the write-pulse is determined dynamically by sensing the status of MTJ cells. The proposed scheme can reduce the power consumption by eliminating unnecessary writing current after the switching has occurred. We also propose a reference cell design, which is optimized for the use in write-circuits. The performance of the proposed circuit was verified by SPICE level simulations of the circuit implemented in a $0.13{\mu}m$ CMOS process.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.3
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• pp.339-344
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• 2014

This paper presents a novel bipolar junction transistor (BJT) based electrostatic discharge (ESD) protection device. This protection device was designed for 20V power clamps and fabricated by a process with Bipolar-CMOS-DMOS (BCD) $0.18{\mu}m$. The current-voltage characteristics of this protection device was verified by the transmission line pulse (TLP) system and the DC BV characteristic was verified by using a semiconductor parameter analyzer. From the experimental results, the proposed device has a trigger voltage of 29.1V, holding voltage of 22.4V and low on-resistance of approximately $1.6{\Omega}$. In addition, the test of ESD robustness showed that the ESD successfully passed through human body model (HBM) 8kV. In this paper, the operational mechanism of this protection device was investigated by structural analysis of the proposed device. In addition, the proposed device were obtained as stack structures and verified.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.601-602
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• 2008

This paper presents pulse-frequency modulation(PFM) to improve the light-load efficiency. The proposed circuit is designed by using the device parameter of standard $0.13{\mu}m$ CMOS process. The performance of proposed circuit is evaluated by HSPICE simulation Measured efficiency in a light-load is measured 78-90 % for 0.1 to 100mA output current.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.537-538
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• 2008

A step-down DC-DC converter with On-chip Compensation for battery-operated portable electronic devices which are designed in 0.18um CMOS standard process. In an effort to improve low load efficiency, this paper proposes the PFM (Pulse Frequency modulation) voltage mode 1MHz switching frequency step-down DC-DC converter with on-chip compensation. Capacitor multiplier method can minimize error amplifier compensation block size by 20%. It allows the compensation block of DC-DC converter be easily integrated on a chip and occupy less layout area. But capacitor multiplier operation reduces DC-DC converter efficiency. As a result, this converter shows maximum efficiency over 87% for the output voltage of 1.8V (input voltage : 3.3V), maximum load current 500mA, and 0.14% output ripple voltage. The total core chip area is $mm^2$.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.476-477
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• 2008

In this paper, high voltage DC- DC boost converters by stacked structure of power transistors are proposed. These stacked power transistors are tolerant to output voltage higher than the process limit for individual CMOS transistors. The proposed circuits were designed in a standard 3.6V, $0.13{\mu}m$.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.499-500
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• 2008

In this paper, we design and implement the monolithic power factor correction IC for system power modules using a high voltage(50V) CMOS process. The power factor correction IC is designed for power applications, such as refrigerator, air-conditioner, etc. It includes low voltage logic, 5V regulator, analog control circuit, high-voltage high current output drivers, and several protection circuits. And also, the designed IC has standby detection function which detects the output power of the converter stage and generates system down signal when load device is under the standby condition. The simulation and experimental results show that the designed IC acts properly as power factor correction IC with efficient protective functions.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.439-440
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• 2008

A high-speed DCO is proposed that uses the negative-skewed delay scheme. The DCO consists of a ring of inverters with each PMOS transistor driven from the output of 3 earlier stage through a set of minimum-sized pass-transistors. The digitization of negative-skewed delay is achieved by selecting pass-transistors turned on and digitizing the gate voltages of the selected pass-transistors. The proposed 7-stage DCO has been simulated using 1.8V, $0.18\;{\mu}m$ TSMC CMOS process to obtain a resolution of 3ps and an operation range of 2.88-5.03GHz.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.441-442
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• 2008

In this paper a Fractional-N frequency synthesizer is designed for UHF RFID readers. It satisfies the ISO/IEC frequency band $(860{\sim}960MHz)$ and is also applicable to mobile RFID readers. It is designed using a $0.18{\mu}$ RF CMOS process. The measured results show that the designed circuit has a phase noise of -103dBc/Hz at 100kHz offset and consumes 9mA from a 1.8V supply. The channel switching time of $10{\mu}s$ over 5MHz transition have been achieved, and the chip size including PADs is $1.8{\times}0.99mm^2$