• Journal of electromagnetic engineering and science
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• 제15권2호
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• pp.63-75
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• 2015

The CMOS power amplifier (PA) is a promising solution for highly-integrated transmitters in a single chip. However, the implementation of PAs using the CMOS process is a major challenge because of the inferior characteristics of CMOS devices. This paper focuses on improvements to the efficiency and linearity of CMOS PAs for modern wireless communication systems incorporating high peak-to-average ratio signals. Additionally, an envelope tracking supply modulator is applied to the CMOS PA for further performance improvement. The first approach is enhancing the efficiency by waveform engineering. In the second approach, linearization using adaptive bias circuit and harmonic control for wideband signals is performed. In the third approach, a CMOS PA with dynamic auxiliary circuits is employed in an optimized envelope tracking (ET) operation. Using the proposed techniques, a fully integrated CMOS ET PA achieves competitive performance, suitable for employment in a real system.

• 전기학회논문지
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• 제58권5호
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• pp.999-1003
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• 2009

We have designed and fabricated a linear drive amplifier with a novel intermodulation distortion(IMD) canceller using $0.18{\mu}m$ CMOS process. The drive amplifier with IMD canceller is composed of a cascode main amplifier and an additional common-source IMD canceller. Since the IMD canceller generates IM3($3^{rd}$-order imtermodulation) signal with $180^{\circ}$ phase difference against the IM3 of the cascode main amplifier, the IM3 power is drastically eliminated. As of the measurement results, $OP_{1dB}$, $OIP_3$, and power-add efficiency are 5.5 dBm, 15.5 dBm, and 21%, respectively. Those are 5 dB, 6 dB, and 13.5% enhanced values compared to a conventional cascode drive amplifier. The IMD3 of the drive amplifier with IMD canceller is enhanced more than 10 dB compared to that of the conventional cascode drive amplifier for input power ranges from -22 to -14 dBm.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2004년도 학술대회지
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• pp.499-502
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• 2004

A two-stage Class E power amplifier operated at 2.44GHz is designed in 0.25-$\mu$m CMOS process for Class-l Bluetooth application. The power amplifier employs c1ass-E topology to exploit its soft-switching property for high efficiency. A preamplifter with common-mode configuration is used to drive the output-stage of Class-E type. The amplifier delivers 20-dBm output power with 70$\%$ PAE (power -added-efficiency) at 2-V supply voltage.

• Journal of information and communication convergence engineering
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• 제17권4호
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• pp.285-289
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• 2019

A 1.9-GHz linear CMOS power amplifier is presented. An adaptive bias circuit (ABC) that utilizes an AC ground to detect the power level of the input signal is proposed to enhance the linearity and efficiency of the power amplifier. The ABC utilizes the second harmonic component as the input to mitigate the distortion of the fundamental signal. The input power level of the ABC was detected at the AC ground located at the V_DD node of the power amplifier. The output of the ABC was fed into the inputs of the power stage. The input signal distortion was mitigated by detecting the input power level at the AC ground. The power amplifier was designed using a 180 nm RFCMOS process to evaluate the feasibility of the application of the proposed ABC in the power amplifier. The measured output power and power-added efficiency were improved by 1.7 dB and 2.9%, respectively.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2008년도 하계종합학술대회
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• pp.545-546
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• 2008

This paper presents a low power CMOS low noise amplifier for UWB applications. To reduce the power consumption, two cascode amplifiers was stacked in DC. Designed with $0.18-{\mu}m$ CMOS technology, the proposed LNA achieves 20dB flat gain, below 3dB noise figure, and the power consumption of 5.2mW from a 1.8 V supply voltage.

• JSTS:Journal of Semiconductor Technology and Science
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• 제12권4호
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• pp.426-432
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• 2012

A fully-integrated low power K-band radar transceiver in 130 nm CMOS process is presented. It consists of a low-noise amplifier (LNA), a down-conversion mixer, a power amplifier (PA), and a frequency synthesizer with injection locked buffer for driving mixer and PA. The receiver front-end provides a conversion gain of 19 dB. The LNA achieves a power gain of 15 dB and noise figure of 5.4 dB, and the PA has an output power of 9 dBm. The phase noise of VCO is -90 dBc/Hz at 1-MHz offset. The total dc power dissipation of the transceiver is 142 mW and the size of the chip is only $1.2{\times}1.4mm^2$.

• 한국전자파학회논문지
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• 제25권9호
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• pp.895-902
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• 2014

본 논문에서는 CMOS $0.18-{\mu}m$ 공정을 이용하여 1.75 GHz 대역에서 동작하는 이단으로 구성된 CMOS 전력증폭기를 설계하였다. 무선통신시스템에 적합한 전력증폭기 설계를 위하여 ADS 모의실험을 통하여 전력이득, 출력 전력, 효율을 각각 28 dB, 27 dBm, 45 %로 설계를 하였다. 실제 제작된 전력증폭기의 성능은 전력 이득, 출력 전력, 효율은 각각 22.9 dB, 24.8 dBm, 41.3 %로 특성을 나타냈으며, 변조된 LTE(Long-Term Evolution) 신호에 대하여 인접 채널 누설비(ACLR)가 -30 dBc 이하를 만족하며, 전력 이득, 출력 전력, 효율이 각각 22.6 dB, 23.1 dBm, 35.1 %의 특성을 나타냈다.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제55권6호
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• pp.287-290
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• 2006

A class-E CMOS RF(Radio frequency) power amplifier with a 1.8 Volt power supply is designed using $0.25{\mu}m$ standard CMOS technology. To drive the class-E power amplifier, a Class-F RF power amplifier is used and the reliability characteristics are studied with a class-E load network. After one year of operating the power amplifier with an RF choke, the PAE(Power Added Efficiency) decreases from 60% to 47% and the output power decreases 29%. However, when a finite DC-feed inductor is used with the load, the PAE decreases from 60% to 53% and the output power decreases only 19%. The simulated results demonstrate that the class-E power amplifier with a finite DC-feed inductor exhibits superior reliability characteristics.

• 한국전자파학회논문지
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• 제27권12호
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• pp.1069-1074
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• 2016

본 논문에서는 TSMC 65 nm CMOS 공정를 이용하여 V-대역 이단 전력증폭기를 설계 및 제작하였다. 수동소자를 사용한 간단한 구조의 정합회로를 구성하였고, 입력과 출력 정합회로를 모두 집적하였다. Pre-distortion 기법을 통해 전력 이득을 보상해 줌으로써 전력증폭기의 선형성을 향상시켰다. 제작된 전력증폭기는 58.8 GHz의 동작 주파수와 1 V의 동작 전압에서 10.4 dB의 전력 이득, 9.7 dBm의 출력 전력 및 20.8 %의 효율 특성을 나타내었다.

• 전력전자학회논문지
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• 제6권1호
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• pp.13-20
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• 2001

본 논문에서는 큰 출력 저항파 기준 전류와의 정합 특성이 우수한 새로운 전류 미러를 제안한다. CMOS 증폭기 회로에서 전원 전압이 작아지는 경우 출럭 전압의 스윙 폭이 전원 전압에 의해 제한되는 단점이 있으므로 제안된 회로는 이런 단점을 해결하기 위해 출력단의 스윙을 키우고, 안정된 동작올 할 수 있도록 한다. 출력단 부하가 큰 경우에 구동 능력을 증대시키고, 작은 전원 전압을 가질 때에도 큰 출력 스윙을 갖는 전류 미러를 시뮬레이션을 통해 가존의 캐스코드 전류 미러와 Regulated 전류 미러의 특성을 비교 및 고찰한다.