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http://dx.doi.org/10.5515/KJKIEES.2014.25.9.895

Design of Two-Stage CMOS Power Amplifier  

Bae, Jongsuk (School of Information and Communication Engineering, Sungkyunkwan University)
Ham, Junghyun (School of Information and Communication Engineering, Sungkyunkwan University)
Jung, Haeryun (School of Information and Communication Engineering, Sungkyunkwan University)
Lim, Wonsub (School of Information and Communication Engineering, Sungkyunkwan University)
Jo, Sooho (School of Information and Communication Engineering, Sungkyunkwan University)
Yang, Youngoo (School of Information and Communication Engineering, Sungkyunkwan University)
Publication Information
The Journal of Korean Institute of Electromagnetic Engineering and Science / v.25, no.9, 2014 , pp. 895-902 More about this Journal
Abstract
This paper presents a 2-stage CMOS power amplifier for the 1.75 GHz band using a $0.18-{\mu}m$ CMOS process. Using ADS simulation, a power gain of 28 dB and an efficiency of 45 % at an 1dB compression point of 27 dBm were achieved. The implemented CMOS power amplifier delivered an output power of up to 24.8 dBm with a power-added efficiency of 41.3 % and a power gain of 22.9 dB. For a 16-QAM uplink LTE signal, the PA exhibited a power gain of 22.6 dB and an average output power of 23.1 dBm with a PAE of 35.1 % while meeting an ACLR(Adjacent Channel Leakage Ratio) level of -30 dBc.
Keywords
Power Amplifier; CMOS; LTE;
Citations & Related Records
Times Cited By KSCI : 1  (Citation Analysis)
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