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Design of Two-Stage CMOS Power Amplifier

이단으로 구성된 CMOS 전력증폭기 설계

  • Bae, Jongsuk (School of Information and Communication Engineering, Sungkyunkwan University) ;
  • Ham, Junghyun (School of Information and Communication Engineering, Sungkyunkwan University) ;
  • Jung, Haeryun (School of Information and Communication Engineering, Sungkyunkwan University) ;
  • Lim, Wonsub (School of Information and Communication Engineering, Sungkyunkwan University) ;
  • Jo, Sooho (School of Information and Communication Engineering, Sungkyunkwan University) ;
  • Yang, Youngoo (School of Information and Communication Engineering, Sungkyunkwan University)
  • 배종석 (성균관대학교 정보통신공학부) ;
  • 함정현 (성균관대학교 정보통신공학부) ;
  • 정혜련 (성균관대학교 정보통신공학부) ;
  • 임원섭 (성균관대학교 정보통신공학부) ;
  • 조수호 (성균관대학교 정보통신공학부) ;
  • 양영구 (성균관대학교 정보통신공학부)
  • Received : 2014.07.01
  • Accepted : 2014.09.05
  • Published : 2014.09.30

Abstract

This paper presents a 2-stage CMOS power amplifier for the 1.75 GHz band using a $0.18-{\mu}m$ CMOS process. Using ADS simulation, a power gain of 28 dB and an efficiency of 45 % at an 1dB compression point of 27 dBm were achieved. The implemented CMOS power amplifier delivered an output power of up to 24.8 dBm with a power-added efficiency of 41.3 % and a power gain of 22.9 dB. For a 16-QAM uplink LTE signal, the PA exhibited a power gain of 22.6 dB and an average output power of 23.1 dBm with a PAE of 35.1 % while meeting an ACLR(Adjacent Channel Leakage Ratio) level of -30 dBc.

본 논문에서는 CMOS $0.18-{\mu}m$ 공정을 이용하여 1.75 GHz 대역에서 동작하는 이단으로 구성된 CMOS 전력증폭기를 설계하였다. 무선통신시스템에 적합한 전력증폭기 설계를 위하여 ADS 모의실험을 통하여 전력이득, 출력 전력, 효율을 각각 28 dB, 27 dBm, 45 %로 설계를 하였다. 실제 제작된 전력증폭기의 성능은 전력 이득, 출력 전력, 효율은 각각 22.9 dB, 24.8 dBm, 41.3 %로 특성을 나타냈으며, 변조된 LTE(Long-Term Evolution) 신호에 대하여 인접 채널 누설비(ACLR)가 -30 dBc 이하를 만족하며, 전력 이득, 출력 전력, 효율이 각각 22.6 dB, 23.1 dBm, 35.1 %의 특성을 나타냈다.

Keywords

References

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