• Journal of IKEEE
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• v.14 no.2
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• pp.51-57
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• 2010

A CMOS rail-to-rail high voltage buffer amplifier is proposed to drive the gamma correction reference voltage of large TFT LCD panels. It is operating by a single supply and only shows current consumption of 0.5mA at 18V power supply voltage. The circuit is designed to drive the gamma correction voltage of 8-bit or 10-bit high resolution TFT LCD panels. The buffer has high slew rate, 0.5mA static current and 1k$\Omega$ resistive and capacitive load driving capability. Also, it offers wide supply range, offset voltages below 50mV at 5mA constant output current, and below 2.5mV input referred offset voltage. To achieve wide-swing input and output dynamic range, current mirrored n-channel differential amplifier, p-channel differential amplifier, a class-AB push-pull output stage and a input level detector using hysteresis comparator are applied. The proposed circuit is realized in a high voltage 0.18um 18V CMOS process technology for display driver IC. The circuit operates at supply voltages from 8V to 18V.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.37-47
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• 2006

This work proposes a 10b 25MS/s $0.8mm^2$ 4.8mW 0.13um CMOS A/D Converter (ADC) for high-performance wireless communication systems such as DVB, DAB and DMB simultaneously requiring low voltage, low power, and small area. A two-stage pipeline architecture minimizes the overall chip area and power dissipation of the proposed ADC at the target resolution and sampling rate while switched-bias power reduction techniques reduce the power consumption of analog amplifiers. A low-power sample-and-hold amplifier maintains 10b resolution for input frequencies up to 60MHz based on a single-stage amplifier and nominal CMOS sampling switches using low threshold-voltage transistors. A signal insensitive 3-D fully symmetric layout reduces the capacitor and device mismatch of a multiplying D/A converter while low-noise reference currents and voltages are implemented on chip with optional off-chip voltage references. The employed down-sampling clock signal selects the sampling rate of 25MS/s or 10MS/s with a reduced power depending on applications. The prototype ADC in a 0.13um 1P8M CMOS technology demonstrates the measured DNL and INL within 0.42LSB and 0.91LSB and shows a maximum SNDR and SFDR of 56dB and 65dB at all sampling frequencies up to 2SMS/s, respectively. The ADC with an active die area if $0.8mm^2$ consumes 4.8mW at 25MS/s and 2.4mW at 10MS/s at a 1.2V supply.

• Journal of IKEEE
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• v.2 no.2 s.3
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• pp.278-284
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• 1998

This paper describes a l0b CMOS A/D converter (ADC) for HDTV applications. The proposed ADC adopts a typical multi-step pipelined architecture. The proposed circuit design techniques are as fo1lows: A selective channel-length adjustment technique for a bias circuit minimizes the mismatch of the bias current due to the short channel effect by supply voltage variations. A power reduction technique for a high-speed two-stage operational amplifier decreases the power consumption of amplifiers with wide bandwidths by turning on and off bias currents in the suggested sequence. A typical capacitor scaling technique optimizes the chip area and power dissipation of the ADC. The proposed ADC is designed and fabricated in s 0.8 um double-poly double-metal n-well CMOS technology. The measured differential and integral nonlinearities of the prototype ADC show less than ${\pm}0.6LSB\;and\;{\pm}2.0LSB$, respectively. The typical ADC power consumption is 119 mW at 3 V with a 40 MHz sampling rate, and 320 mW at 5 V with a 50 MHz sampling rate.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.4
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• pp.492-498
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• 2017

In this paper, we integrate a divide-by-3 injection-locked frequency divider (ILFD) in CMOS technology with a $0.18-{\mu}m$ BiCMOS process. We propose a self-injection technique that utilizes harmonic conversion to improve the locking range, phase-noise, and input sensitivity simultaneously. The proposed self-injection technique consists of an odd-to-even harmonic converter and a feedback amplifier. This technique offers the advantage of increasing the injection efficiency at even harmonics and thus realizes the low-power implementation of an odd-order division ILFD. The measurement results using the proposed self-injection technique show that the locking range is increased by 47.8% and the phase noise is reduced by 14.7 dBc/Hz at 1-MHz offset frequency with the injection power of -12 dBm. The designed divide-by-3 ILFD occupies $0.048mm^2$ with a power consumption of 18.2-mW from a 1.8-V power supply.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.42 no.5 s.305
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• pp.43-50
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• 2005

This paper describes some IC(integrated circuits) design and implementation techniques of low power multi-band Gm-C bandpass filter for body composition analyzer. Proposed BPF(bandpass filter) can be selected from three bands(20 KHz, 50 KHz, 100 KHz) by control signal. To minimize die area, a simple center frequency tuning scheme is used. And to reduce power consumption, operational transconductance amplifier operated in the sub-threshold region is adopted. The proposed BPF is implemented with 0.35 um 2-poly 3-metal standard CMOS technology Chip area is $626.42um\;{\times}\;475.8um$ and power consumption is 700 nW@100 KHz.

• Journal of IKEEE
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• v.22 no.3
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• pp.786-792
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• 2018

A third-order sigma-delta modulator with the architecture of cascade of integrator feedback (CIFB) is proposed for an analog-digital converter used in low-power sensor interfaces. It consists of three switched-capacitor integrators using a gain-enhanced current-mirror-based amplifier, a single-bit comparator, and a non-overlapped clock generator. The proposed sigma-delta analog modulator with over-sampling ratio of 160 and maximum SNR of 90.45 dB is implemented using $0.11-{\mu}m$ CMOS process with 1.2-V supply voltage. The area and power consumption of the sigma-delta analog modulator are $0.145mm^2$ and $341{\mu}W$, respectively.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.37 no.6
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• pp.25-34
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• 2000

This paper describes design of a 250-Mbps 10-channel optical receiver array for parallel optical interconnection with the general-purpose CMOS technology The optical receiver is one of the most important building blocks to determine performance of the parallel optical interconnection system. The chip in CMOS technology makes it possible to implement the cost-effective system also. Each data channel consists of analog front-end including the integrated photo-detector and amplifier chain, digital block with D-FF and off-chip driver. In addition, the chip includes PLL (Phase-Lock Loop) for synchronous data recovery. The chip was fabricated in a 0.65-${\mu}{\textrm}{m}$ 2-poly, 2-metal CMOS technology. Power dissipation of each channel is 330㎽ for $\pm$2.5V supply.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.4
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• pp.499-504
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• 2017

A UHF CMOS variable gain low-noise amplifier (LNA) is designed for mobile digital TV tuners. The proposed LNA adopts a feedback topology to cover a wide frequency range from 474 to 868 MHz, and it supports the notch filter function for the interoperability with the GSM terminal. In order to handle harmonic distortion by strong interferers, the gain of the proposed LNA is step-controlled while keeping almost the same input impedance. The proposed LNA is implemented in a $0.11{\mu}m$ CMOS process and consumes 6 mA at a 1.5 V supply voltage. In the measurement, it shows the power gain of greater than 16 dB, NF of less than 1.7 dB, and IIP3 of greater than -1.7 dBm for the UHF band.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.65 no.5
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• pp.831-835
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• 2016

In this paper, a dual-channel feed-forward transimpedance(TIA) array is realized in a standard $0.18-{\mu}m$ CMOS technology which exploits automatic gain control function to provide 40-dB input dynamic range for either detecting targets nearby or sensing imminent danger situations. Compared to the previously reported conventional feed-forward TIA, the proposed automatic-gain-control feed-forward TIA(AFF-TIA) extends the input dynamic range 25 dB wider by employing a 4-level automatic gain control circuit. Measured results demonstrate the linearly varying transimpedance gain of 47 to $72dB{\Omega}$, input dynamic range of 1:100, the bandwidth of $${\geq_-}670MHz$$, the equivalent input referred noise current spectral density of 6.9 pA/${\surd}$HZ, the maximum sensitivity of -26.8 dBm for $10^{-12}BER$, and the power consumption of 27.6 mW from a single 1.8-V supply. The dual-channel chip occupies the area of $1.0{\times}0.73mm^2$ including I/O pads.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.12 s.354
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• pp.65-73
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• 2006

This work presents a 14b 200KS/s $0.87mm^2$ 1.2mW 0.18um CMOS algorithmic A/D converter (ADC) for intelligent sensors control systems, battery-powered system applications simultaneously requiring high resolution, low power, and small area. The proposed algorithmic ADC not using a conventional sample-and-hold amplifier employs efficient switched-bias power-reduction techniques in analog circuits, a clock selective sampling-capacitor switching in the multiplying D/A converter, and ultra low-power on-chip current and voltage references to optimize sampling rate, resolution, power consumption, and chip area. The prototype ADC implemented in a 0.18um 1P6M CMOS process shows a measured DNL and INL of maximum 0.98LSB and 15.72LSB, respectively. The ADC demonstrates a maximum SNDR and SFDR of 54dB and 69dB, respectively, and a power consumption of 1.2mW at 200KS/s and 1.8V. The occupied active die area is $0.87mm^2$.