• Proceedings of the IEEK Conference
• /
• summer
• /
• pp.221-224
• /
• 2004

This paper proposed an ultra low-power CMOS exponential voltage-mode circuit using the Pseudo-exponential function for realizing the exponential characteristics. The proposed circuit provides high dB-linear output voltage range at low-voltage applications. In a $0.25\;\mu m$ CMOS process, the simulations show more than 35 dB output voltage range and 26 dB with the linearity error less than $\pm0.5\;dB.$ The average current consumption is less than 80 uA. The proposed circuit can be used for the design of an extremely low-power variable gain amplifier (VGA) and automatic gain control (AGC).

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.21 no.4
• /
• pp.321-328
• /
• 2008

In this paper, variable gain amplifier(VGA) with a gain slope controller has been proposed and verified by circuit simulations and measurements. The proposed VGA has a gain control, gain slope switch and variable gain range. The input source coupled pair with diode connected load is used for VGA gain stage. The gain slope controller with switch can control VGA gain slope. The proposed VGA is fabricated in $0.18{\mu}m$ CMOS process for multi -standard wireless receiver. The proposed two stage VGA consumes min. 2.0 mW to max. 2.6 mW in gain control range and gives input IP3 of -3.77 dBm and NF of 28.7 dB at 1.8 V power supply under -25 dBm, 1 MHz input. The proposed VGA has 37 dB(-16 dB $\sim$ 21 dB) variable gain range, and 8 dB gain range control per 0.3 V control voltage, and can provide variable gain, positive and negative gain slope control, and gain range control. This VGA characteristics provide design flexibility in multi-standard wireless receiver.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.43 no.7 s.349
• /
• pp.13-19
• /
• 2006

A 5Gb/s cross coupled transimpedance amplifier (TIA) & limiting amp(LA), regulated cascode(RGC) is realized in a 0.18$\mu$m CMOS technology for optical printed circuit board applications. The optical receiver demonstrates $92.8db{\Omega}$ transimpedance and limiting amplifier gain, 5Gb/s bandwidth for 0.5pF photodiode capacitance, and 9.74mW power dissipation from 1.8V, 2.4V supply. Input stage impedance is $50{\Omega}$. The circuit was implemented on an optical PCB, and the 5Gb/s data output signal was measured with a good data eye opening.

• Journal of Sensor Science and Technology
• /
• v.5 no.6
• /
• pp.25-34
• /
• 1996

In this paper, we have designed signal conditioning circuitry for piezoresistive pressure sensor. Signal conditioning circuitry consists of voltage reference circuit for sensor driving voltage and instrument amplifier for sensor signal amplification. Signal conditioning circuitry is simulated using HSPICE in a single poly double metal $1.5\;{\mu}m$ BiCMOS technology. Simulation results of band-gap reference circuit showed that temperature coefficient of $21\;ppm/^{\circ}C$ at the temperature range of $0\;{\sim}\;70^{\circ}C$ and PSRR of 80 dB. Simulation results of BiCMOS amplifier showed that dc voltage gain, offset voltage, CMRR, CMR and PSRR are outperformed to CMOS and Bipolar, but power dissipation and noise voltage were more improved in CMOS than BiCMOS and Bipolar. Designed signal conditioning circuitry showed high input impedance, low offset and good CMRR, therefore, it is possible to apply sensor and instrument signal conditioning circuitry.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.18 no.5
• /
• pp.777-784
• /
• 2023

A sense amplifier is an essential peripheral circuit for designing a memory and is used to sense a small differential input signal and amplify it into digital signal. In this paper, a high-speed sense amplifier applicable to in-memory computing circuits is proposed. The proposed circuit reduces sense delay time through transistor Mtail that provides an additional discharge path and improves the circuit performance of the sense amplifier by applying m-GDI (: modified Gate Diffusion Input). Compared with previous structure, the sense delay time was reduced by 16.82%, the PDP(: Power Delay Product) by 17.23%, the EDP(: Energy Delay Product) by 31.1%. The proposed circuit was implemented using TSMC's 65nm CMOS process, while its feasibility was verified through SPECTRE simulation in this study.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.11 no.4
• /
• pp.1222-1228
• /
• 2010

This paper presents a design of the CMOS LDO regulator with a fast transient response for a high speed PMIC(power management integrated circuit). Proposed LDO regulator circuit consists of a reference voltage circuit, an error amplifier and a power transistor. 2-stage wide-band OTA buffer between error amplifier and power transistor is added for a good output stability. Although conventional source follower buffer structure is simple, it has a narrow output swing and a low S/N ratio. In this paper, we use a 2-stage wide-band OTA instead of source follower structure for a buffer. From HSPICE simulation results using a $0.5{\mu}m$ CMOS standard technology, simulation results were 16 mV/V line regulation and 0.007 %/mA load regulation.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.47 no.1
• /
• pp.52-59
• /
• 2010

This paper proposes a high-resolution and high-frame rate CMOS image sensor with column-wise cyclic ADC. The proposed ADC uses the sharing techniques of OTAs and capacitors for low-power consumption and small silicon area. The proposed ADC was verified implementing the prototype chip as QVGA image sensor. The measured maximum frame rate is 120 fps, and the power consumption is 130 mW. The power supply is 3.3 V, and the die size is $4.8\;mm\;{\times}\;3.5\;mm$. The prototype chip was fabricated in a 2-poly 3-metal $0.35-{\mu}m$ CMOS process.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.26 no.4
• /
• pp.278-283
• /
• 2013

This paper presents a design and fabrication of 0.5 V two stage operational amplifier. The proposed operational amplifier utilizes body-driven differential input stage and self-cascode current mirror structure. Cadence Virtuoso is used for layout and the layout data is verified by LVS through Mentor Calibre. The proposed two stage operational amplifier is fabricated using $0.13{\mu}m$ CMOS process and operation at 0.5 V is confirmed. Measured low frequency small signal gain of operational amplifier is 50 dB, power consumption is $29{\mu}W$ and chip area is $75{\mu}m{\times}90{\mu}m$.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.18 no.5
• /
• pp.769-776
• /
• 2023

In this paper, we designed an MLSA(Match-line Sense Amplifier) for low-power CAM(Content Addressable Memory). By using the MLSA and precharge controller, we reduced power consumption during CAM operation by employing a selective match-line charging technique to mitigate power consumption caused by mismatch. Additionally, we further reduced power consumption due to leakage current by terminating precharge early when a mismatch occurs during the search operation. The designed circuit exhibited superior performance compared to the existing circuits, with a reduction of 6.92% and 23.30% in power consumption and propagation delay time, respectively. Moreover, it demonstrated a significant decrease of 29.92% and 52.31% in product-delay-product (PDP) and energy-delay-product (EDP). The proposed circuit was validated using SPECTRE simulation with TSMC 65nm CMOS process.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.31 no.3A
• /
• pp.356-359
• /
• 2006

A monolithic SiGe HBT variable gain driver amplifier(VGDA) with high dB-linear gain control and high linearity has been developed as a driver amplifier with ground-shielded microstrip lines for 5-GHz transmitters. The VGDA consists of three blocks such as the cascode gain-control stage, fixed-gain output stage, and voltage control block. The circuit elements were optimized by using the Agilent Technologies' ADSs. The VGDA was implemented in STMicroelectronics' 0.35${\mu}m$ Si-BiCMOS process. The VGDA exhibits a dynamic gain control range of 34 dB with the control voltage range from 0 to 2.3 V in 5.15-5.35 GHz band. At 5.15 GHz, maximum gain and attenuation are 10.5 dB and -23.6 dB, respectively. The amplifier also produces a 1-dB gain-compression output power of -3 dBm and output third-order intercept point of 7.5 dBm. Input/output voltage standing wave ratios of the VGDA keep low and constant despite change in the gain-control voltage.