• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.224-227
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• 1999

This paper presents a design of the real-time preprocessor for CMOS image sensor suitable to the digital camera applications. CMOS image sensor offers some advantages in on-chip integration, system power reduction, and low cost. However, it has a lower-quality image than CCDs. We describe an image enhancement algorithm, which includes color interpolation, color correction, gamma correction, sharpening, and automatic exposure control, to compensate for this disadvantage, and present its efficient hardware architecture to implement on the real-time processor. The presented real-time preprocessor was designed using VHDL, and it contains about 19.2K logic gates. We also implement our system on FPGA chips in order to provide the real-time adjustment and it was successfully tested.

• Journal of the Optical Society of Korea
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• v.19 no.6
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• pp.658-664
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• 2015

Lens designers generally refer to flat image fields and attempt to minimize the field curvature. Present-day CMOS image sensors for mobile phone cameras, however, are not flat, but curved. Sometimes it is necessary to generate an intentional field curvature according to the degree and direction of the CMOS image-sensor’s curvature. This paper presents the degree of curvature of a CMOS image sensor measured using an interferometer, and proposes an effective compensation method that minimizes the net field curvature through optimizing the air gap between lens elements, which is demonstrated using simulations and experiments.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.33 no.10
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• pp.93-97
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• 2005

We have developed the FDSS (Fine Digital Sun Sensor) for the space technology of the STSAT-2 (Seience & Technology Satellite 2). The FDSS is firstly developed by using CMOS image sensor(CIS) in South Korea. The FDSS consists of the optics part, FPGA(Field Programable Gate Array) part, and MCU(Micro controller unit)part. This paper will focus on the optical characteristics of the optics part and describe the configuration of FDSS with the design of aperture. We also analyze the characteristic of optics about the pixel of the CMOS image sensor.

• Journal of Sensor Science and Technology
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• v.14 no.6
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• pp.387-394
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• 2005

In order to design SOI CMOS image sensors, SOI MOSFET model parameters were extracted using the equation of bulk MOSFET model parameters and were optimized using SPICE level 2. Simulated I-V characteristics of the SOI NMOSFET using the extracted model parameters were compared to the experimental I-V characteristics of the fabricated SOI NMOSFET. The simulation results agreed well with experimental results. A unit pixel for SOI CMOS image sensors was designed and was simulated for the PPS, APS, and logarithmic circuit using the extracted model parameters. In these CMOS image sensors, a nano-wire MOSFET photodetector was used. The output voltage levels of the PPS and APS are well-defined as the photocurrent varied. It is confirmed that SOI CMOS image sensors are faster than bulk CMOS image sensors.

• Journal of Astronomy and Space Sciences
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• v.18 no.3
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• pp.231-238
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• 2001

A prototype CMOS (complementary metal oxide semiconductor) imaging system has been built and the possibility of applying to the application to astronomical observations has been investigated. The CCD (charge coupled device) image sensor has been the mainstay of image capture and astronomical imaging for the last 30 years, but CMOS devices have shown rapidly increasing success and have been adapted to many commercial imaging systems . Although the photometric performances and system noise of CMOS sensors are lower than that of CCD image sensors, CMOS Imaging system can be used to obtain general image capture for astronomical applications.

• Journal of IKEEE
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• v.24 no.4
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• pp.942-949
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• 2020

In this paper, we propose an improved algorithmic ADC for CMOS Image Sensor that is suitable for a column-parallel readout circuit. The algorithm of the conventional algorithmic ADC is modified so that it can operate as a single amplifier while being independent of the capacitor ratio and insensitive to the gain of the op-amp, and it has a high conversion efficiency by using an adaptive biasing amplifier. The proposed ADC is designed with 0.18-um Magnachip CMOS process, Spectre simulation shows that the power consumption per conversion speed is reduced by 37% compared with the conventional algorithmic ADC.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.4
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• pp.388-396
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• 2012

In this paper, a $320{\times}240$ pixel, 80 frame/s CMOS image sensor with a low power dual correlated double sampling (CDS) scheme is presented. A novel 8-bit hold-and-go counter in each column is proposed to obtain 10-bit resolution. Furthermore, dual CDS and a configurable counter scheme are also discussed to realize efficient power reduction. With these techniques, the digital counter consumes at least 43% and at most 61% less power compared with the column-counters type, and the frame rate is approximately 40% faster than the double memory type due to a partial pipeline structure without additional memories. The prototype sensor was fabricated in a Samsung $0.13{\mu}m$ 1P4M CMOS process and used a 4T APS with a pixel pitch of $2.25{\mu}m$. The measured column fixed pattern noise (FPN) is 0.10 LSB.

• Journal of IKEEE
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• v.11 no.1 s.20
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• pp.38-45
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• 2007

A new 8-bit single-slope ADC using analog RAMP generator with digitally controllable dynamic range has been proposed and simulated for column level or per-pixel CMOS image sensor application. The conversion gain of ADC can he controlled easily by using frequency divider with digitally controllable diviber ratio, coarse/fine RAMP with class-AB op-amp, resistor strings, decoder, comparator, and etc. The chip area and power consumption can be decreased by simplified analog circuits and passive components. Proposed frequency divider has been implemented and verified with 0.65um, 2-poly, 2-metal standard CMOS process. And the functional verification has been simulated and accomplished in a 0.35$\mu$m standard CMOS process.

• Current Optics and Photonics
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• v.7 no.2
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• pp.200-206
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• 2023

Near-infrared (NIR) sensing technology using CMOS image sensors is used in many applications, including automobiles, biological inspection, surveillance, and mobile devices. An intuitive way to improve NIR sensitivity is to thicken the light absorption layer (silicon). However, thickened silicon lacks NIR sensitivity and has other disadvantages, such as diminished optical performance (e.g. crosstalk) and difficulty in processing. In this paper, a pixel structure for NIR sensing using a stacked CMOS image sensor is introduced. There are two photodetection layers, a conventional layer and a bottom photodiode, in the stacked CMOS image sensor. The bottom photodiode is used as the NIR absorption layer. Therefore, the suggested pixel structure does not change the thickness of the conventional photodiode. To verify the suggested pixel structure, sensitivity was simulated using an optical simulator. As a result, the sensitivity was improved by a maximum of 130% and 160% at wavelengths of 850 nm and 940 nm, respectively, with a pixel size of 1.2 ㎛. Therefore, the proposed pixel structure is useful for NIR sensing without thickening the silicon.

• International Journal of Aeronautical and Space Sciences
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• v.13 no.2
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• pp.260-265
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• 2012

Satellite devices for fine attitude control of the Science & Technology Satellite-2 (STSAT-2). Based on the mission requirements of STSAT-2, the conventional analog-type sun sensors were found to be inadequate, motivating the development of a compact, fast and fine digital sun sensor (FDSS). The FDSS uses a CMOS image sensor and has an accuracy of less than 0.03degrees, an update rate of 5Hz and a weight of less than 800g. A pinhole-type aperture is substituted for the optical lens to minimize its weight. The target process speed is obtained by utilizing the Field Programmable Gate Array (FPGA), which acquires images from the CMOS sensor, and stores and processes the image data. The sensor accuracy is maintained by a rigorous centroid algorithm. This paper describes the FDSS designs, realizations, tests and calibration results.