Browse > Article
http://dx.doi.org/10.7471/ikeee.2020.24.4.942

Capacitor Ratio-Independent and OP-Amp Gain-Insensitive Algorithmic ADC for CMOS Image Sensor  

Hong, Jaemin (Dept. of Electronics Engineering, Kookmin University)
Mo, Hyunsun (Dept. of Electronics Engineering, Kookmin University)
Kim, Daejeong (Dept. of Electronics Engineering, Kookmin University)
Publication Information
Journal of IKEEE / v.24, no.4, 2020 , pp. 942-949 More about this Journal
Abstract
In this paper, we propose an improved algorithmic ADC for CMOS Image Sensor that is suitable for a column-parallel readout circuit. The algorithm of the conventional algorithmic ADC is modified so that it can operate as a single amplifier while being independent of the capacitor ratio and insensitive to the gain of the op-amp, and it has a high conversion efficiency by using an adaptive biasing amplifier. The proposed ADC is designed with 0.18-um Magnachip CMOS process, Spectre simulation shows that the power consumption per conversion speed is reduced by 37% compared with the conventional algorithmic ADC.
Keywords
CMOS Image Sensor(CIS); column-parallel readout; algorithmic adc; ratio-independent; gain-insensitive; adaptive biasing;
Citations & Related Records
연도 인용수 순위
  • Reference
1 B. S. Carlson, "Comparison of modern CCD and CMOS image sensor technologies and systems for low resolution imaging," in IEEE Proc. Sensors, pp.171-176, 2002. DOI: 10.1109/ICSENS.2002.1037011   DOI
2 Hongjie Zhu, Milin Zhang, Yuanming Suo, Trac D. Tran, Jan Van der Spiegel, "Design of a Digital Address-Event Triggered Compressive Acquisition Image Sensor," IEEE Transactions on Circuits and Systems-I:Regular Papers, vol.63, no.2, pp.191-199, 2016. DOI: 10.1109/TCSI.2015.2512719   DOI
3 Fei Wang, Liqiang Han, Albert J. P. Theuwissen, "Development and Evaluation of a Highly linear CMOS Image Sensor With a Digitally Assisted Linearity Calibration," IEEE Journal of Solid-State Circuits, vol.53, no.10, pp.2970-2981, 2018. DOI: 10.1109/JSSC.2018.2856252   DOI
4 N. Cho, B. Song, K. Kim, and J. Burm, S. W. Han, "A VGA CMOS Image Sensor with 11-bit column parallel single-slope ADCs," IEEE International SoC Design Conference, pp.25-27. DOI: 10.1109/SOCDC.2010.5682981   DOI
5 S. Matsuo et al., "8.9-megapixel video image sensor with 14-b column-parallel SA-ADC," IEEE Trans. Electron Devices, vol.56, no.11, pp. 2380-2389, 2009. DOI: 10.1109/TED.2009.2030649   DOI
6 S.-Y. Chin, C.-J. Wu, "A CMOS Ratio-Independent and Gain-Insensitive Algorithmic Analog-to-Digital converter," IEEE Journal of Solid-State Circuits, vol.31, no.8, pp.1201-1207, 1996. DOI: 10.1109/4.508271   DOI
7 S. Lim, J. Cheon, Y. Chae, W. Jung, D.-H. Lee, M. Kwon, K. Yoo, S. Ham, and G. Han, "A 240-frames/s 2.1-Mpixel CMOS image sensor with column-shared cyclic ADCs," IEEE Journal of Solid-State Circuits, vol.46, no.9, pp.2073-2083, 2011. DOI: 10.1109/JSSC.2011.2144010   DOI
8 P. W. Li, M. J. Chin, P. R. Gray, and R. Castello, "A Ratio-Independent Algorithmic Analog-to-Digital Conversion Technique," IEEE Journal of Solid-State Circuits, vol.SC-19, no.6, pp.828-836, 1984. DOI: 10.1109/JSSC.1984.1052233   DOI
9 K. Nagaraj, T. R. Viswanathan, K. Singhal, and J. Vlach, "Switched-capacitor circuits with reduced sensitivity to amplifier gain," IEEE Transactions on Circuits and Systems, vol.CAS-34, no.5, pp.571-574, 1987. DOI: 10.1109/TCS.1987.1086170   DOI
10 S. Baswa, A. J. Lopez-Martin, J. Ramirez-Angulo, and R. G. Carvajal, "Low-voltage micropower super class AB CMOS OTA," Electron. Lett., vol.40, pp.216-217, 2004. DOI: 10.1049/el:20040166   DOI
11 S.-Y. Chin, C.-J. Wu, "The Flipped Voltage Follower: A Useful Cell for Low-Voltage Low-Power Circuit Design," IEEE Transactions on Circuits and Systems- I:Regular Papers, vol.52, no.7, pp.1276-1291, 2005. DOI: 10.1109/TCSI.2005.851387   DOI
12 T. B. Cho and P. R. Gray, "A 10 b, 20 Msample/s, 35mW pipeline A/D converter," IEEE Journal of Solid-State Circuits, vol.30, no.3, pp. 166-172, 1995. DOI: 10.1109/4.364429   DOI