• Journal of IKEEE
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• v.7 no.2 s.13
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• pp.172-180
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• 2003

Based on simulation results and accompanying analysis, we suggest a thyristor-type ESD protection device structure suitable for implementation in standard CMOS processes to reduce the parasitic capacitances added to the input nodes, which is very important in CMOS RF ICs. We compare DC breakdown characteristics of the suggested device to those of a conventional NMOS protection device to show the benefits of using the suggested device for ESD protection. The characteristic improvements are demonstrated and the corresponding mechanisms are explained based on simulations. Structure dependencies are also examined to define the optimal structure. AC simulation results are introduced to estimate the magnitude of reduction in the added parasitic capacitance when using the suggested device for ESD protection. The analysis shows a possibility of reducing the added parasitic capacitance down to about 1/40 of that resulting with a conventional NMOS protection transistor, while maintaining robustness against ESD.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.14 no.3
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• pp.189-196
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• 1989

In this paper, BICMOS gate array technology that has CMOS devices for logic applications and bipolar devices for driver applications is presented. An optimized poly gate p-well CMOS process is chosen to fabricate the BICMOS gate array system and the basic concepts to design these devices are to improve the characteristics of bipolar & CMOS device with simple process technology. As the results hFE value is 120(Ic=1mA) for transistor, and there is no short channel effects for CMOS devices which have Leff to 1.25um and 1.35um for n-channel, respectively, 0.8nx gate delay time of 41 stage ring oscillators is obtained.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.10 no.7
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• pp.1526-1531
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• 2009

This paper describes the design of a 5th order Elliptic CMOS Gm-C low-voltage filter for the RFID reader IC. The designed filter is composed of CMOS differential transconductors by parallel gain circuits to improve the gain of the conventional self-biased differential amplifier. The filter is designed to operate in low-voltage 1.8V to meet the specification of the RFID reader filter. The results of HSPICE simulation using 1.8V-0.18${\mu}m$CMOS processing parameter showed that the designed 5th order Elliptic low-pass filter satisfied the cutoff frequency of 1.35MHz given by the design specification.

• Journal of IKEEE
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• v.26 no.1
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• pp.111-118
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• 2022

In this paper, we studied 4H-SiC CMOS that can be integrated with high-voltage SiC power devices. After designing the CMOS on a 4H-SiC substrate, we compared the electrical characteristics with the reliability of high temperature operation by TCAD simulation. In particular, it was confirmed that changing HfO₂ as the gate dielectric for reliable operation at high temperatures improves the thermal properties compared to SiO₂. By researching SiC CMOS devices, we can integrate high-power SiC power devices with SiC CMOS for excellent performance in terms of efficiency and cost of high-power systems.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.40 no.12
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• pp.2503-2510
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• 2015

This paper presents a single-phase energy measurement IC to measure electric power quantities. The entire IC includes two programmable gain amplifiers (PGAs), two ${\sum}{\Delta}$ modulators, a reference circuit, a low-dropout (LDO) regulator, a temperature sensor, a filter unit, a computation engine, a calibration control unit, registers, and an external interface block. The proposed energy measurement IC is fabricated with $0.18-{\mu}m$ CMOS technology and housed in a 32-pin quad-flat no-leads (QFN) package. It operates at a clock speed of 4,096 kHz and consumes 10 mW in 3.3 V supply.

• Journal of IKEEE
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• v.18 no.4
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• pp.586-592
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• 2014

In this paper, high efficiency power management IC(PMIC) with DT-CMOS(Dynamic threshold voltage Complementary MOSFET) switching device is presented. PMIC is controlled PWM control method in order to have high power efficiency at high current level. The DT-CMOS switch with low on-resistance is designed to decrease conduction loss. The control parts in Buck converter, that is, PWM control circuit consist of a saw-tooth generator, a band-gap reference(BGR) circuit, an error amplifier, comparator circuit, compensation circuit, and control block. The saw-tooth generator is made to have 1.2MHz oscillation frequency and full range of output swing from supply voltage(3.3V) to ground. The comparator is designed with two stage OP amplifier. And the error amplifier has 70dB DC gain and $64^{\circ}$ phase margin. DC-DC converter, based on current mode PWM control circuits and low on-resistance switching device, achieved the high efficiency nearly 96% at 100mA output current. And Buck converter is designed along LDO in standby mode which fewer than 1mA for high efficiency. Also, this paper proposes two protection circuit in order to ensure the reliability.

• Journal of Sensor Science and Technology
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• v.3 no.3
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• pp.16-21
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• 1994

A 3-terminal pin-type photosensor with gate contrail is fabricated using standard silicon CMOS IC process. The photosensor of a $100{\mu}m{\times}120{\mu}m$ size has dark current less than 1nA and its breakdown voltage is -14V with a depletion capacitance 0.75 pF at -5V reverse bias. Responsivity at 0V gate voltage is 0.25A/W at $0.633{\mu}m$ wavelength, 0.19A/W at $0.805{\mu}m$. Responsivity increases with increasing gate voltage. The integrated circuit of photosensor and CMOS inverter shows $22K{\Omega}$ transimpedance and photocurrent of $90{\mu}A$ switchs the output state of digital inverter without additional amplifier.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.10A
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• pp.1588-1596
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• 1999

This paper describes a signaling processor IC for land mobile radio systems. This IC generates CTSS tone or DCS code signals for signaling between the land mobile radio systems and decodes them to open the audio path. The CTSS tone or DCS code signals occupy the subaudio band and are transmitted with voice signal. The audio and subaudio paths consist of switched capacitor filters. The IC has been implemented in 0.6-$\mu\textrm{m}$ 2-poly 3-metal CMOS process. The chip size is 3 mm$\times$4.3 mm and total current is about 3.4 ㎃ at 3.3 V.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.8A
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• pp.1252-1258
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• 1999

This paper describes a COMS IF transceiver IC for 10-MHz bandwidth wireless local loops. It interfaces between the RF section and the digital MODEM section and performs the IF-to-baseband (Rx) and baseband-to-IF (Tx) frequency conversions. The chip incorporates variable gain amplifiers, phase-locked loops, low pass filters, analog-to-digital and digital-to-analog converters. It has been implemented in a 0.6 -${\mu}{\textrm}{m}$ 2-poly 3-metal CMOS process. The phase-locked loops include voltage-controlled oscillators, dividers, phase detectors, and charge pumps on chip. The only external complonents are the filter and the varactor-tuned LC tank circuit. The chip size is 4 mm $\times$ 4 mm and the total supply current is about 57 mA at 3.3 V.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.537-540
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• 2004

In this paper, CMOS A/D converter with 6bit 2GSPS Nyquist input at 1.8V is designed. In order to obtain the resolution of 6bit and the character of high-speed operation. we present an Interpolation type architecture. In order to overcome the problems of high speed operation further a novel encoder, a circuit for the Reference Fluctuation, an Averaging Resistor and a Track & Hold for the improved SNR are proposed. The proposed Interpolation ADC consists of Track & Holt four resistive ladders with 64 taps, 32 comparators and digital blocks. The proposed ADC is based on 0.18um 1-poly 3-metal N-well CMOS technology, and it consumes 145mW at 1.8V power supply.