• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.10
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• pp.34-39
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• 2016

A low-voltage, low-power analog front-end IC for neural recording implant devices is presented. The proposed IC consists of a low-noise neural amplifier and a programmable active bandpass filter to process neural signals residing in the band of 1 Hz to 5 kHz. The neural amplifier is based on a source-degenerated folded-cascode operational transconductance amplifier (OTA) for good noise performance while the following bandpass filter utilizes a low-power current-mirror based OTA with programmable high-pass cutoff frequencies from 1 Hz to 300 Hz and low-pass cutoff frequencies from 300 Hz to 8 kHz. The total recording analog front-end provides 53.1 dB of voltage gain, $4.68{\mu}Vrms$ of integrated input referred noise within 1 Hz to 10 kHz, and noise efficiency factor of 3.67. The IC is designed using $18-{\mu}m$ CMOS process and consumes a total of $3.2{\mu}W$ at 1-V supply voltage. The layout area of the IC is $0.19 mm^2$.

• Proceedings of the IEEK Conference
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• 2004.08c
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• pp.455-459
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• 2004

Electrostatic discharge(ESD) is a serious reliability concern. It causes approximately most of all field failures of integrated circuits. Inevitably, future IC technologies will shrink the dimensions of interconnects, gate oxides, and junction depths, causing ICs to be increasingly susceptible to ESD-induced damage [1][2][3]. This thesis shows the optimization of the ESD protection circuit based on the tested results of MM (Machine Model) and HBM (Human Body Model), regardless of existing Reference in fully silicided 0.18 um CMOS process. His thesis found that, by the formation of silicide in a source and drain contact, the dimensions around the contact had a less influence on the ESD robustness and the channel width had a large influence on the ESD robustness [8].

• Proceedings of the KIEE Conference
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• 1987.07b
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• pp.1525-1527
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• 1987

This paper describe the KUIC-CEX, an automated CMOS layout verification program which extracts circuit connectivity, MOSFET dimensions, and parasitic capacitance for CIF(1) file. In the KUIC-CEX, Bitmap approach(2, 3) is used for basic operation. Since the output of this program is the Input file format of PSPICE, we can easily verify the layout of circuit. This program is written in C language.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.2
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• pp.36-47
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• 1998

Low power circuit techniques have been developed to realize the highest possible performance of embedded SRAM at 1V power supply with$0.5\mu\textrm{m}$ single threshold CMOS technology in which the unbalance between NMOS and PMOS threshold voltages is utilized to optimize the low power CMOS IC design. To achieve the best trade-off between the transistor drivability and the subthreshold current increase, the ground potential of memory array is raised to suppressthe subthreshold current. The problems of lower cellstability and bit-line dealy increase due to the enhanced array ground potential are evaluated to be controlled within the allowable range by careful circuit design. 160MHz, 128kb embedded SRAM with 3.4ns access time is demonstrated with the power consumption of 14.8mW in active $21.4{mu}W$ in standby mode at 1V power supply.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.923-926
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• 2003

This paper presents a novel low voltage reference circuit under the MOS threshold voltage(V$_{th}$) in standard CMOS process. It is based on the weighted difference of the gate-source voltages of an NMOS and a PMOS operating in saturation region. The voltage reference is designed for low power OLED driver ICs. The proposed circuit is designed using 0.35${\mu}{\textrm}{m}$ CMOS technology. The minimum supply voltage is 2V, and the typical temperature coefficient is 99.6ppm/ C.C.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.895-898
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• 1999

Recently, small signal modeling of CMOS device becomes more difficult because the design rule goes into deep submicron. De-embedding of substrate parameters is important in order to use CMOS devices at RF frequencies. In this paper, we suggest a new de-embedding model with refined physical meaning and accuracy. In GaAs IC’s, the substrate is almost an insulator but Si substrate has the semiconducting characteristics. It offers some troubles if it is treated like GaAs substrate. The conducting substrate is modeled with five resistances, which leads to very accurate modeling so long as the pad layout is symmetrical. Frequency range is up to 39㎓ and fitting accuracy is as small as 0.00037 on least square errors.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.212-215
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• 1999

High-speed device is essential to optoelectric IC for optical storage system such as CD-ROM, DVD, and to ADC for high-speed communication system. This paper represents the BiCMOS process which contains high-speed SAVEN bipolar transistor and analyzes the frequency and switching characteristics of it briefly. Finally, to prove that the SAVEN device is adequate for high-speed system, latched comparator operating at 500MHz is designed with the SPICE parameter extracted from BiCMOS device simulation.

• JSTS:Journal of Semiconductor Technology and Science
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• v.7 no.2
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• pp.94-97
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• 2007

The desin and implementation of a CMOS analog integrated circuit that provides dual-mode modulations, PWM for active clamp reset converter and PFM for LLC resonant converter, is described. The proposed controller is capable of implementing programmable soft start and current-mode control with compensating ramp for PWM and frequency shifting soft start for PFM. Also it provides delay time for both modes. PWM mode is implemented by active clamp reset converter and PFM mode is implemented by LLC resonant convereter, respectively. The chip is fabricated using the 0.6um high voltage CMOS process.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.8
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• pp.49-63
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• 1997

This paper presents a current sensor that detects defects in CMOS integrated circuits using the current testing technique. The current sensor is built in a CMOS integrated circuit to test an abnormal current. The proposed circuit has a very small impact on the performance of the circuit under test during the normal mode. In the testing mode, the proposed circuit detects the abnormal current caused by permanent manufacturing defects and determines whether the circuit under test is defect-free or not. The proposed current sensor is simple and requires no external voltage and current sources. Hence, the circuit has less area and performance degradation, and is more efficient than any previous works. The validity and effectiveness are verified through the HSPICE simulation on circuits with defects.

• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.1984-1987
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• 2002

This paper describes the design and implementation of a single-chip digitally synthesized 0-35MHz agile function generator. The chip comprises an integrated direct digital synthesizer (DDS) with a 10-bit on- chip digital-to-analog converter (DAC) using an n-well single-poly triple-metal 0.5-$\mu\textrm{m}$ CMOS technology. The main features of the chip include maximum clock frequency of 100 MHz at 3.3-V supply voltage, 32-bit frequency tuning word resolution, 12-bit phase tuning word resolution, and an on-chip 10-bit DAC. The chip provides sinusoidal, ramp, saw-tooth, and random waveforms with phase and frequency modulation, and power-down function. At 100-MHz clock frequency, the chip covers a bandwidth from dc to 35 MHz in 0.0233-Hz frequency steps with 190-ns frequency switching speed. The complete chip occupies 12-mm$^2$die area and dissipates 0.4 W at 100-MHz clock frequency.