• Journal of the Korean Institute of Telematics and Electronics
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• v.24 no.4
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• pp.652-657
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• 1987

This paper describes an application of CMOS Gate Array Integrated Cricuits to the implementation of three functional units: A Multiplexer, Time Switch, and Demultiplexer in the Switching Network and Digital Line Concentrator of TDX-1 system, which is a fully digital time division electronic switching system in Korea. The application of CMOS Gate Array Integrated Circuits significantly improves the overall system performance in terms of power consumption, cost, size, reliability, and timing margin, etc.

• Proceedings of the Korea Society for Industrial Systems Conference
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• 2002.06a
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• pp.195-199
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• 2002

This paper describes the effect of substrate back bias of CMOS Inverter. When the substrate back bias applied in body, the MOS transistor threshold voltage increased and drain saturation current decreased. The back gate reverse bias or substrate bias has been widely utilized and the following advantage has suppressing subthreshold leakage, lowering parasitic junction capacitance, preventing latch up or parasitic bipolar transistor, etc. When the reverse voltage applied substrate, this paper stimulated the propagation delay time CMOS inverter.

• Journal of IKEEE
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• v.8 no.1 s.14
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• pp.33-38
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• 2004

A multi-valued logic(MVL) pass gate is an important element to configure multi-valued logic. In this paper, we designed the Quaternary MIN(QMIN)/negated MIN(QNMIN) gate, the Quaternary MAX(QMAX)/negated MAX(QNMAX) gate using double pass-transistor logic(DPL) with neuron $MOS({\nu}MOS)$ threshold gate. DPL is improved the gate speed without increasing the input capacitance. It has a symmetrical arrangement and double-transmission characteristics. The threshold gates composed by ${\nu}MOS$ down literal circuit(DLC). The proposed gates get the valued to realize various multi threshold voltages. In this paper, these circuits are used 3V power supply voltage and parameter of 0.35um N-Well 2-poly 4-metal CMOS technology, and also represented HSPICE simulation results.

• Journal of the Korean Institute of Telematics and Electronics
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• v.21 no.6
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• pp.78-84
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• 1984

We propose a new algorithm which detects stuck-open faults in CMOS circuits without being affected by time skews not using additional circuits. That is, the Domino CMOS circuit structure is used as circuit configurations and the clocking gate in this circuit is modeled as one branch, then test sequence is generated by using the transition test. Also, it is verified by applying this algorithm implemented in VAX II/780 to arbitrary CMOS circuits that all of stuck-open faults which were not detected because of time skews in conventional methods is detected.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.3
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• pp.177-184
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• 2014

In chemical vapor deposition(CVD) tungsten silicide(WSix) dual poly gate(DPG) scheme, we observed the fluorine effects on gate oxide using the electrical and physical measurements. It is found that in fluorine-rich WSix NMOS transistors, the gate thickness decreases as gate length is reduced, and it intensifies the roll-off properties of transistor. This is because the fluorine diffuses laterally from WSix to the gate sidewall oxide in addition to its vertical diffusion to the gate oxide during gate re-oxidation process. When the channel length is very small, the gate oxide thickness is further reduced due to a relative increase of the lateral diffusion than the vertical diffusion. In PMOS transistors, it is observed that boron of background dopoing in $p^+$ poly retards fluorine diffusion into the gate oxide. Thus, it is suppressed the fluorine effects on gate oxide thickness with the channel length dependency.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.05a
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• pp.788-791
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• 2010

We design 64-bit ROM IP for RFID tag chips using printed CMOS non-volatile memory IP design technology for a printed CMOS process. The proposed 64-bit ROM circuit is using ETRI's $0.8{\mu}m$ CMOS porocess, and is expected to reduce process complexity and cost of RFID tag chips compared to that using a conventional silicon fabrication based on a complex lithography process because the poly layer in a gate terminal is using printing technology of imprint process. And a BL precharge circuit and a BL sense amplifier is not required for the designed cell circuit since it is composed of a transmission gate instead of an NMOS transistor of the conventional ROM circuit. Therefore an output datum is only driven by a DOUT buffer circuit. The Operation current and layout area of the designed ROM of 64 bits with an array of 8 rows and 8 columns using $0.8{\mu}m$ ROM process is $9.86{\mu}A$ and $379.6{\times}418.7{\mu}m^2$.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.12
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• pp.198-208
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• 1995

BiCMOS circuit consist of CMOS part which constructs logic function, and bipolar part which drives output load. Test to detect stuck-open faults in BiCMOS circuit is important, since these faults do sequential behavior and are represented as transition faults. In this paper, proposes a method for efficiently detecting transistor stuck-open faults in BiCMOS circuit by transforming them into slow-to=rise transition and slow-to-fall transition. In proposed method, BiCMOS circuit is transformed into equivalent gate-level circuit by dividing it into pull-up part which make output 1, and pull-down part which make output 0. Stuck-open faults in transistor are modelled as transition fault in input line of gate level circuit which is transformed from given circuit. Faults are detceted by using pull-up part gate level circuit when expected value is '01', or using pull-down part gate level circuit when expected value is '10'. By this method, transistor stuck-open faults in BiCMOS circuit are easily detected using conventional gate level test generation algorithm for transition fault.

• Journal of the Korean Institute of Telematics and Electronics
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• v.21 no.5
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• pp.55-60
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• 1984

With the advancement of CMOS technology, it has become attractive to employ complex gate structures in realizing digital circuits. A new test generation algorithm for CMOS complex gates to detect all stuck-open and stuck-on faults considering internal gate response and unknown state is proposed. Minimal and complete set can be derived by this algorithm. Also, it is verified that such a test set is generated applying this algorithm to arbitrary CMOS complex gates by computer.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.11
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• pp.56-64
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• 2007

We developed the first automatic design system targeting a promising hybrid CMOS-Nanoelectronics Architecture called CMOL. The CMOL architecture uses NOR gates to implement combinational logic. In this hybrid CMOS-nanoelectronics architecture, logical functions and the interconnections share the nanoelectronics hardware resource. Towards automating the CMOL physical design process, we developed a model for the CMOL architecture, formulated the placement and routing problems for the CMOL architecture subject to the unique CMOL specific constraints, and solved it by combining a placement algorithm with a gate assignment algorithm in a loop. We validated the proposed approach by implementing several industrial strength designs.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.4
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• pp.65-72
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• 2013

This paper presents design methodology for Memristor-CMOS circuits and its application to primitive IPs design. We proposed a Memristor model and designed basic elements, Memristor AND/OR gates. The primitive IPs based on a Memristor-CMOS technology is proposed for a Memristive system design. The netlists of IPs are extracted from the layouts of Memristor-CMOS and is verified with SPICE-like Memristor model under $0.18{\mu}m$ CMOS technology. As a result, an example design Memristor-CMOS full adder has only 47.6 % of silicon area compare to the CMOS full-adder.