• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.1
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• pp.1-9
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• 2007

Digital Multimedia Broadcasting is the next generation broadcasting service which enables various digital multimedia contents, i.e., audio and video, and data access for mobile users. However, due to the bandwidth limitation, the spatial resolution is limited to CIF(Common Interleaved Frame). The Advanced Terrestrial DMB (AT-DMB) secures additional bandwidth by adopting hierarchical modulation transmission technology and provides high data rate and quality for mobile multimedia broadcasting services with scalable video coding(SVC). This paper proposes scalable video coding technology for AT-DMB which enables high quality mobile multimedia broadcasting services that exceeds current DMB service's quality and contents capability.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.44 no.5
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• pp.73-83
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• 2007

In this paper, we propose macroblock(MB)-based adaptive interpolation filter method for improving coding efficiency in H.264/AVC. In the proposed method, nine separable two-dimensional(2D) interpolation filters are applied for precisely compensating motions in various directions. The optimal cost function which considers the bit rate and distortion for coding the MB is defined. The filter is adaptively selected per MB for minimizing the defined cost function. In the experimental results, the proposed method shows more excellent in coding efficiency than the conventional methods for the various standard $QCIF(176{\times}144)/CIF(352{\times}288)$ video test sequences. It leads to about 6.25%(1 reference frame) and 3.46%(5 reference frames) bit rate reduction on average compared to the H.264/AVC.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.11
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• pp.29-36
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• 2003

In this paper, an efficient VLSI architecture for DCTQ module, which consists of 2D-DCT, quantization, AC/DC prediction block, scan conversion, inverse quantization and 2D-IDCT, is presented. The architecture of the module is designed to handle a macroblock data within 1064 cycles and suitable for MPEG-4 video codec handling 30 frame CIF image for both encoder and decoder simultaneously. Only single 1-D DCT/IDCT cores are used for the design instead of 2-D DCT/IDCT, respectively. 1-bit serial distributed arithmetic architecture is adopted for 1-D DCT/IDCT to reduce the hardware area in this architecture. To reduce the power consumption of DCTQ modu1e, we propose the method not to operate the DCTQ modu1e exploiting the SAE(sum of absolute error) value from motion estimation and cbp(coded block pattern). To reduce the AC/DC prediction memory size, the memory architecture and memory access method for AC/DC prediction block is proposed. As the result, the maximum utilization of hardware can be achieved, and power consumption can be minimized. The proposed design is operated on 27MHz clock. The experimental results show that the accuracy of DCT and IDCT meet the IEEE specification.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.11C
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• pp.1541-1550
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• 2004

In this paper, we propose an advanced hardware architecture for fast multi-resolution motion estimation of the video coding standard MPEG-1,2 and MPEG-4 AVC. We describe the algorithm and derive hardware architecture emphasizing the importance of area for low cost and fast operation by using the shared memory, the special ram architecture, the motion vector for 4 pixel x 4 pixel, the spiral search and so on. The proposed architecture has been verified by ARM-interfaced emulation board using Excalibur Altera FPGA and also by ASIC synthesis using Samsung 0.18 m CMOS cell library. The ASIC synthesis result shows that the proposed hardware can operate at 140 MHz, processing more than 1,100 QCIF video frames or 70 4CIF video frames per second. The hardware is going to be used as a core module when implementing a complete MPEG-4 AVC video encoder ASIC for real-time multimedia application.

• Journal of KIISE:Computer Systems and Theory
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• v.31 no.5_6
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• pp.305-320
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• 2004

Moving object segmentation is a fundamental function for content-based application. Moving object edges are produced by matching the detected moving edges with the current frame edges. But we can often experience the object edge disconnectedness due to coincidence of similarity between the object and background colors or the decrease of movement of moving object. The edge disconnectedness is a serious problem because it degrades the object visual quality so conspicuously That it sometimes makes it inadequate to perform content-based coding. We have solved this problem by developing a robust and comprehensive edge linking algorithm. And we also developed an automatic moving object segmentation algorithm. These algorithms can produce the completely linked moving object edge boundary and the accurate moving object segmentation. These algorithms can process CIF 30 frames/sec in a PC. These algorithms can be used for the MPEG-4 content-based coding.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.3
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• pp.621-627
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• 2010

This paper proposes an efficient architecture of Inter layer up-sampling in decoder for SVC(scalable video coding). A register bank for horizontal and vertical up-sampling and interpolation units are designed, by introducing the proposed architecture, 41% memory bandwidth is reduced compared to JSVM. For real-time operation for HD 6 layer decoder having CIF, SD, HD resolution for CGS layer, the hardware is designed to operate at 127MHz. The gate count is about 3000.

• Journal of the Korean Institute of Telematics and Electronics
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• v.22 no.1
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• pp.14-21
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• 1985

In this paper, a new pitch extraction method, the area comparison method, is proposed. By the speech production model, the area of the first peak on a pitch interval of speech signals is emphasized. By using the above characteristics, this method have more advantages than the others for pitch extraction. The defective decision caused by an impulsive noise is minimized and the pre-filtering is not necessary for this rr ethos, because the integration of signals takes place in the process.

• 한국정보디스플레이학회:학술대회논문집
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• 2004.08a
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• pp.1024-1026
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• 2004

We have developed the five mask $PMOS^1$ and the six mask CMOS process architecture for poly-Si TFT. In order to have a competitive process with that for a-Si TFT, the simple co-planar electrode structure whose data line electrode and pixel electrode are on the same plane was adopted. In addition, RGB + White four color $technology^2$ were applied to achieve high aperture ratio and transmittance. Using the aforementioned process architecture and four color technology, 2.0 inch qCIF transmissive micro-reflectance (TMR) device was successfully fabricated.

• Proceedings of the Korean Information Science Society Conference
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• 2006.10c
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• pp.544-547
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• 2006

본 논문에서는 디지털콘텐츠 식별자 연계 표준인 UCI 정보를 이용하여 효율적인 디지털 콘텐츠의 관리가 가능한 무손실 비디오 워터마킹 기법을 이용하였다. 제안한 기법은 각 비디오 프레임의 히스토그램의 특정 구간의 화소값을 수정함으로써 워터마크를 삽입한다. 4CIF 크기의 테스트 시퀀스를 통한 실험결과 화질의 열화가 적으면서도 UCI 정보를 100% 왜곡없이 검출이 가능하였으며, 원본 디지털 비디오 콘텐츠도 모든 테스트 시퀀스에서 100% 복원이 가능하였다. 제안한 기법은 디지털 비디오에 UCI 정보를 직접 삽입하여 메타데이터가 없을 경우 콘텐츠만으로도 콘텐츠의 식별이 가능하고 콘텐츠로부터 추출한 UCI 정보를 통하여 효율적인 관리가 가능하면서 유사시 원본 콘텐츠를 손실없이 복원이 가능할 수 있어 영화, 방송 등의 다양한 비디오 콘텐츠의 관리를 위해 응용될 수 있다.

• Proceedings of the KIEE Conference
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• 1987.07b
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• pp.1525-1527
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• 1987

This paper describe the KUIC-CEX, an automated CMOS layout verification program which extracts circuit connectivity, MOSFET dimensions, and parasitic capacitance for CIF(1) file. In the KUIC-CEX, Bitmap approach(2, 3) is used for basic operation. Since the output of this program is the Input file format of PSPICE, we can easily verify the layout of circuit. This program is written in C language.