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http://dx.doi.org/10.6109/jkiice.2010.14.3.621

An Efficient Architecture of Inter Layer Up-sampling in Scalable Video Decoder  

Ki, Dae-Wook (부산대학교 전자전기공학과)
Kim, Jae-Ho (부산대학교 전자전기공학과)
Publication Information
Journal of the Korea Institute of Information and Communication Engineering / v.14, no.3, 2010 , pp. 621-627 More about this Journal
Abstract
This paper proposes an efficient architecture of Inter layer up-sampling in decoder for SVC(scalable video coding). A register bank for horizontal and vertical up-sampling and interpolation units are designed, by introducing the proposed architecture, 41% memory bandwidth is reduced compared to JSVM. For real-time operation for HD 6 layer decoder having CIF, SD, HD resolution for CGS layer, the hardware is designed to operate at 127MHz. The gate count is about 3000.
Keywords
Scalable Video Coding; SVC; Inter layer Up-sampling; JSVM;
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