• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.6
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• pp.615-628
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• 2015

CGRA (Coarse-Grained Reconfigurable Architecture) based multi-core architecture can be considered as a suitable solution for the fault-tolerant computing. However, there have been a few research projects based on fault-tolerant CGRA without exploiting the strengths of CGRA as well as their works are limited to single CGRA. Therefore, in this paper, we propose two approaches to enable exploiting the inherent redundancy and reconfigurability of the multi-CGRA for fault-recovery. One is a resilient inter-CGRA fabric that is ring-based sharing fabric (RSF) with minimal interconnection overhead. Another is a novel intra/inter-CGRA reconfiguration technique on RSF for maximizing utilization of the resources when faults occur. Experimental results show that the proposed approaches achieve up to 94% faulty recoverability with reducing area/delay/power by up to 15%/28.6%/31% when compared with completely connected fabric (CCF).

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.3
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• pp.284-299
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• 2014

Coarse-grained reconfigurable architecture (CGRA)-based multi-core architecture aims at achieving high performance by kernel level parallelism (KLP). However, the existing CGRA-based multi-core architectures suffer from much energy and performance bottleneck when trying to exploit the KLP because of poor resource utilization caused by insufficient flexibility. In this work, we propose a new ring-based sharing fabric (RSF) to boost their flexibility level for the efficient resource utilization focusing on the kernel-stream type of the KLP. In addition, based on the RSF, we introduce a novel inter-CGRA reconfiguration technique for the efficient pipelining of kernel-stream on CGRA-based multi-core architectures. Experimental results show that the proposed approaches improve performance by up to 50.62 times and reduce energy by up to 50.16% when compared with the conventional CGRA-based multi-core architectures.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.2
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• pp.307-311
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• 2015

In this paper, we propose an efficient fault-recovery technique for CGRA (Coarse-Grained Reconfigurable Architecture) based multi-core architecture. The proposed technique is intra/inter-CGRA co-reconfiguration technique based on a ring-based sharing fabric (RSF) and it enables exploiting the inherent redundancy and reconfigurability of the multi-CGRA for fault-recovery. Experimental results show that the proposed approaches achieve up to 73% fault recoverability when compared with completely connected fabric (CCF).

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.3
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• pp.207-220
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• 2011

Coarse-grained reconfigurable architecture (CGRA) based embedded systems aims to achieve high system performance with sufficient flexibility to map a variety of applications. However, the CGRA has been considered as prohibitive one due to its significant area/power overhead and performance bottleneck. In this work, I propose reconfigurable multi-array architecture to reduce power/area and enhance performance in configurable embedded systems. The CGRA-based embedded systems that consist of hierarchical configurable computing arrays with varying size and communication speed were examined for multimedia and other applications. Experimental results show that the proposed approach reduces on-chip area by 22%, execution time by up to 72% and reduces power consumption by up to 55% when compared with the conventional CGRA-based architectures.

• Proceedings of the Korea Information Processing Society Conference
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• 2009.04a
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• pp.875-876
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• 2009

최근에 응용프로그램의 복잡도가 증가함에 따라 이를 빠르게 처리하기 위하여 각종 멀티미디어 SoC에서 Coarse Grained Reconfigurable Architecture (CGRA)들이 사용되고 있다. CGRA가 제공하는 병렬성을 극대화하기 위한 많은 어플리케이션 매핑 알고리즘이 연구되어 왔으나 CGRA에서 소모되는 전력을 줄이기 위한 노력은 거의 없는 상태이다. 이러한 문제를 극복하기 위해 본 논문에서는 기존의 매핑 알고리즘을 기반으로 누설전력을 줄이기 위한 방법에 대해 다루고자 한다.

• The KIPS Transactions:PartA
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• v.19A no.1
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• pp.17-22
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• 2012

The demand of high performance processor is soaring due to the extending of mobile and small electronic device market. CGRA(Coarse Grained Reconfigurable Architecture) is the processor satisfying both of performance and low-power demands and a great alternative of ASIC that can be reconfigured. This paper presents a novel low-power mapping algorithm that optimizes the number of used computation resource in the mapping phase by considering data transfer time. Compared with previous mapping algorithm, ours reduce energy consumption by up to 73%, and 56.4% on average.

• Journal of IKEEE
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• v.17 no.4
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• pp.418-427
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• 2013

In this paper, we propose a parallel deblocking filter algorithm for H.264/AVC video standard. The deblocking filter has different filter processes according to boundary strength (BS) and each filter process requires various conditional calculations. The order of filtering makes it difficult to parallelize deblocking filter calculations. The proposed deblocking filter algorithm is performed on PRAGRAM which is a 1-D coarse grained reconfigurable architecture (CGRA). Each filter calculation is accelerated using uni-directional pipelined architecture of PRAGRAM. The filter selection and the conditional calculations are efficiently performed using dynamic reconfiguration and conditional reconfiguration. The parallel deblocking filter algorithm uses 225 cycles to process a macroblock and it can process a full HD image at 150 MHz.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2014.06a
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• pp.166-168
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• 2014

Coarse-grained reconfigurable architectures (CGRAs) present a potential of high compute throughput with energy efficiency. A CGRA consists of an array of functional units (FU), which communicate with each other through an interconnect network containing transmission nodes and register files. To achieve high performance from the software solutions mapped onto CGRAs, modulo scheduling of loops is generally employed. One of the key challenges in modulo scheduling for CGRAs is to explicitly handle routings of operands from a source to a destination operations through various routing resources. Existing modulo schedulers for CGRAs are slow because finding a valid routing is generally a searching problem over a large space, even with the guidance of well-defined cost metrics. Applications in traditional embedded multimedia domains are regarded relatively tolerant to a slow compile time in exchange of a high quality solution. However, many rapidly growing domains of applications, such as 3D graphics, require a fast compilation. Entrances of CGRAs to these domains have been blocked mainly due to its long compile time. We attack this problem by utilizing patternized routes, for which resources and time slots for a success can be estimated in advance when a source operation is placed. By conservatively reserving predefined resources at predefined time slots, future routings originated from the source operation are guaranteed. Experiments on a real-world 3D graphics benchmark suite show that our scheduler improves the compile time up to 6000 times while achieving average 70% throughputs of the state-of-art CGRA modulo scheduler, edge-centric modulo scheduler (EMS).

• Proceedings of the Korea Information Processing Society Conference
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• 2011.11a
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• pp.24-27
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• 2011

재구성형 프로세서는 높은 성능과 낮은 전력 소모, 재구성이 가능하다는 점에서 갈수록 높아지는 모바일 및 소형 전자기기 시장의 요구 조건을 충족시키기에 적합한 특성을 가지고 있다. 이 논문에서는 아키텍처 명세 언어인 SoarDL 언어를 확장하여 재구성형 프로세서를 효과적으로 기술할 수 있는 방법과 함께, 이를 바탕으로 재구성형 프로세서를 위한 컴파일러를 생성할 수 있는 방안을 제시한다.

• The Journal of Engineering Geology
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• v.28 no.4
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• pp.661-672
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• 2018

Radon concentration was measured in a total of 5,453 groundwater samples from wells across Korea. The radon concentrations showed the values ranging from 0.1 Bq/L to 7,218.7 Bq/L, with a median of 48.8 Bq/L which is lower than those of other countries having similar geological conditions. The distribution of radon concentrations was lognormal. The median value is high in the granite areas (63.5-105.1 Bq/L) while it is low in the sedimentary rocks and Cheju volcanic area (16.0-20.3 Bq/L). When grouping the groundwater with well depth, the median radon value is high in weathering and/or upper bedrock zone (61.4 Bq/L) while it is low in alluvium and/or weathering zone (28.5 Bq/L). About 17.7% of the total samples exceeded 148 Bq/L of USEPA guideline value. The exceeding radon ratio more than 148 Bq/L in groundwater is highest in Jurassic granite area, however, the exceeding radon rates more than 300 Bq/L and 500 Bq/L are highest in CGRA area.