• Journal of information and communication convergence engineering
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• v.9 no.3
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• pp.305-309
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• 2011

This paper proposes a new rotational frequency detector (RFD) for phase-locked loop (PLL) or clock and data recovery (CDR) applications for fast frequency acquisition. The proposed RFD uses the four states finite state machine (FSM) model to accelerate the frequency acquisition time. It is modeled and simulated with MATLAB Simulink. The functionalities of the proposed RFD are examined and the results are compared to those of a conventional RFD. The proposed RFD's frequency acquisition time is four times faster than that of a conventional one. The proposed RFD incorporated with a phase detector (PD) in PLL or CDR is expected to improve the frequency and phase acquisition performance later greatly.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.3
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• pp.185-192
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• 2013

In this paper, a clock and data recovery (CDR) circuit that supports triple data rates of 1.62, 2.7, and 5.4 Gbps for DisplayPort 1.2 standard is described. The proposed CDR circuit covers three different operating frequencies with a single VCO switching the operating frequency by the 3-bit digital code. The prototype chip has been designed and verified using a 65 nm CMOS technology. The recovered-clock jitter with the data rates of 1.62/2.7/5.4 Gbps at $2^{31}$-1 PRBS is measured to 7/5.6/4.7 $ps_{rms}$, respectively, while consuming 11 mW from a 1.2 V supply.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.61 no.11
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• pp.1695-1699
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• 2012

This paper is proposed all digital wide-range clock and data recovery circuit. The Proposed clock data recovery circuit is possible input data rate which is suggested is wide-range that extends from 100Mb/s to 3Gb/s and used an phase error detector which can use a way of over-sampling a data by using a 1/2-rate multi-phase clock and phase rotator which is regular size per $2{\pi}$/16 and can make a phase rotation. So it could make the phase rotating in range of input data rate. Also all circuit is designed as a digital which has a specificity against a noise. This circuit is designed to 0.13um CMOS process and verified simulation to spectre tool.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2003.11a
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• pp.136-139
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• 2003

A clock recovery circuit for a 40 Gb/s optical receiver has been designed and implemented. The clock recovery circuit consists of signal amplifiers, a nonlinear circuit with diodes, and a bandpass filter Before implementing the 40 Gb/s clock recovery circuit, a 10 Gb/s clock recovery circuit has been successfully implemented and tested. With the 40 Gb/s clock recovery circuit, when a 40 Gb/s NRZ signal of -10 dBm was applied to the input of the circuit, the 40 GHz clock was recovered with the -20 dBm output power after passing through the nonlinear circuit. The output signal from the nonlinear circuit passes through a narrow-band filter, and then amplified. The implemented clock recovery circuit is planned to be used for the input of a phase locked loop to further stabilize the recovered clock signal and to reduce the clock jitter.

• 한국정보통신설비학회:학술대회논문집
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• 2005.08a
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• pp.154-158
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• 2005

In this paper, we design optical receiver composed of CDR(clock and data recovery), SA(sense amp), TIA(transimpe dence amplifier), and decision circuit. The optical receiver can be classified to two main block, one is Deserializer composed of CDR and SA, another is PD receiver composed of preamplifier(샴), peak detector, etc. In this paper, we propose CDR using delayed data topology that could improve defects of existing CDR. The optical receiver that is proposed in this paper has the role of translation a 1.25 Gb/s optical signal to $10{\times}125 Mb/s$ array electric signals. This optical receiver is verified by simulator(hspice) using 0.35 um CMOS technology.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.2
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• pp.19-24
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• 2007

With recent advancement of high-speed, multi-gigabit data transmission capabilities, serial links have been more widely adopted in industry than parallel links. Since the parallel link design forces its transmitter to transmit both the data and the clock to the receiver at the same time, it leads to hardware's intricacy during high-speed data transmission, large power consumption, and high cost. Meanwhile, the serial links allows the transmitter to transmit data only with no synchronized clock information. For the purpose, clock and data recovery circuit becomes a very crucial key block. In this paper, a 5.4Gbps half-rate bang-bang CDR is designed for the applications of high-speed graphic DRAM interface. The CDR consists of a half-rate bang-bang phase detector, a current-mirror charge-pump, a 2nd-order loop filter, and a 4-stage differential ring-type VCO. The PD automatically retimes and demultiplexes the data, generating two 2.7Gb/s sequences. The proposed circuit is realized in 66㎚ CMOS process. With input pseudo-random bit sequences (PRBS) of $2^{13}-1$, the post-layout simulations show 10psRMS clock jitter and $40ps_{p-p}$ retimed data jitter characteristics, and also the power dissipation of 80mW from a single 1.8V supply.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2005.11a
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• pp.191-196
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• 2005

A low-cost, high-performance 40 Gb/s clock recovery module using a phase-locked loop(PLL) for a 40 Gb/s optical receiver has been designed and implemented. It consists of a clock recovery circuit, a RF mixer and frequency discriminator for phase/frequency detection, a DR-VCO, a phase shifter, and a hold circuit. The recovered 40 GHz clock is synchronized with a stable 10 GHz DR-VCO. The clock stability and jitter characteristics of the implemented PLL-based clock recovery module has shown to significantly improve the performance of the conventional open-loop type clock recovery module with DR filter. The measured peak-to-peak RMS jitter is about 230 fs. When input signal is dropped, the 40 GHz clock is generated continuously by hold circuit. The implemented clock recovery module can be used as a low-cost and high-performance receiver module for 40 Gb/s commercial optical network.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2002.11a
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• pp.394-397
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• 2002

A design study of phase detectors for the 2.5 Gb/s CDR circuit using a standard 0.18-${\mu}{\textrm}{m}$ CMOS process has been performed. The targeted CDR is based on the phase-locked loop and thus it consists of a phase detector, a charge pump, a LPF, and a VCO. For high frequency operation of 2.5 Gb/s, phase detector and charge pump, which accurately compare phase errors to reduce clock jitter, are critical for designing a reliable CDR circuit. As a phase detector, the Hogge phase detector is selected but two transistors are added to improve the performance of the D-F/F. The charge pump was also designed to be placed indirectly input and output.

• ETRI Journal
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• v.30 no.2
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• pp.268-274
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• 2008

This paper proposes an open-loop clock recovery circuit (CRC) using two high-Q dielectric resonator (DR) filters for 39.8 Gb/s and 42.8 Gb/s dual-mode operation. The DR filters are fabricated to obtain high Q-values of approximately 950 at the 40 GHz band and to suppress spurious resonant modes up to 45 GHz. The CRC is implemented in a compact module by integrating the DR filters with other circuits in the CRC. The peak-to-peak and RMS jitter values of the clock signals recovered from 39.8 Gb/s and 42.8 Gb/s pseudo-random binary sequence (PRBS) data with a word length of $2^{31}-1$ are less than 2.0 ps and 0.3 ps, respectively. The peak-to-peak amplitudes of the recovered clocks are quite stable and within the range of 2.5 V to 2.7 V, even when the input data signals vary from 150 mV to 500 mV. Error-free operation of the 40 Gb/s-class optical receiver with the dual-mode CRC is confirmed at both 39.8 Gb/s and 42.8 Gb/s data rates.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.4
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• pp.506-517
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• 2015

This paper presents a 1.248 Gb/s - 2.918 Gb/s low-power receiver MIPI-DigRF M-PHY with a fully digital frequency detection loop. MIPI-DigRF M-PHY should be operated in a very short training time which is $0.01{\mu}s$ the for HS-G2B mode. Because of this short SYNC pattern, clock and data recovery (CDR) should have extremely fast locking time. Thus, the quarter rate CDR with a fully digital frequency detection loop is proposed to implement a fast phase tracking loop. Also, a low power CDR architecture, deserializer and voltage controlled oscillator (VCO) are proposed to meet the low power requirement of MIPI-DigRF M-PHY. This chip is fabricated using a $0.11{\mu}m$ CMOS process, and the die area is $600{\mu}m{\times}250{\mu}m$. The power consumption of the receiver is 16 mW from the supply voltage of 1.1 V. The measured lock time of the CDR is less than 20 ns. The measured rms and peak jitter are $35.24ps_{p-p}$ and $4.25ps_{rms}$ respectively for HS-G2 mode.