Browse > Article
http://dx.doi.org/10.5370/KIEE.2012.61.11.1695

Design of Wide-range All Digital Clock and Data Recovery Circuit  

Go, Gwi-Han (전북대 전자공학과)
Jung, Ki-Sang (전북대 전자공학과)
Kim, Kang-Jik (전북대 전자공학과)
Cho, Seong-Ik (전북대 전자공학과)
Publication Information
The Transactions of The Korean Institute of Electrical Engineers / v.61, no.11, 2012 , pp. 1695-1699 More about this Journal
Abstract
This paper is proposed all digital wide-range clock and data recovery circuit. The Proposed clock data recovery circuit is possible input data rate which is suggested is wide-range that extends from 100Mb/s to 3Gb/s and used an phase error detector which can use a way of over-sampling a data by using a 1/2-rate multi-phase clock and phase rotator which is regular size per $2{\pi}$/16 and can make a phase rotation. So it could make the phase rotating in range of input data rate. Also all circuit is designed as a digital which has a specificity against a noise. This circuit is designed to 0.13um CMOS process and verified simulation to spectre tool.
Keywords
Wide-range CDR(Clock Data Recovery); All digital;
Citations & Related Records

Times Cited By SCOPUS : 0
연도 인용수 순위
  • Reference
1 S. J. Song, N. J. Cho, H. J. Yoo, "A 0.2-mW 2-Mb/s Digital Transceiver Based on Wideband Signaling for Human Body Communications" IEEE Journal, Solid-state circuits, Vol. 42, No. 9, pp. 2021-2034, September 2007.   DOI   ScienceOn
2 Fuji Yang, Jay H. O'Neill, David Inglis, and Joseph Othmer, "A CMOS Low-Power Multiple 2.5-3.125-Gb/s Serial Link Macrocell for High IO Bandwidth Network ICs", IEEE Journal, Solid-state circuits, Vol. 37, No. 12, pp. 1813-1821, December 2002.   DOI   ScienceOn
3 S. Y. Lee, H. R. Lee, Y. H. Kwak, B. J. Yoo, D. Shim, C. Kim, and D. K. Jeong, "250 Mbps.5 Gbps wide-range CDR with digital vernier phase shifting and dual mode control in 0.13 m CMOS," in Proc. IEEE Asian Solid-State Circuits Conf., 2010, pp. 185-188.
4 Y. S. Seo, J. W. Lee, H. J. Kim, C. S. Yoo, J. J. Lee, C. S. Jeong, "A 5-Gbit/s Clock- and Data-Recovery Circuit with 1/8-Rate Linear Phase Detector in 0.18-um CMOS Technology", IEEE Transactions on Circuits and Systems-II: Express Biefs, VOL. 56, NO. 1, January 2009.
5 R. B. Staszewski, K. Mhammad, D. Leipold, C. M. Hung, Y. C. Ho, J. L. Wallberg, C. Fernando, K. Maggio, R. Staszewski, T. Jung, J. Koh, S. John, Irene Y. Deng, V. Sardam, O. Moreira-Tamayo, V. Mayega, R. Katz, O. Fridmanm, O. E. Eliezerm, E. De-Obaldia, P. T. Balsara, "All-Digital TX Frequency synthesizer and Discrete-Time Receiver for Bluetooth Radio in 130-nm CMOS" IEEE Journal, Solid-state circuits, Vol. 39, No. 12, pp. 2278-2291, December 2004.   DOI   ScienceOn
6 Y. S. Abdalla, M. I. Elmasry, "A 4Gb/s 1:16 DEMUX Using An All-Static 0.18-um CMOS Logic", ICM, pp. 9-11, December 2003.