• Journal of the Institute of Electronics Engineers of Korea SC
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• v.40 no.3
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• pp.208-214
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• 2003

Because the digital control includes microprocessor different from an analog control, the digital control enables to monitor internal parameters of DC-DC converter and to control output voltage remotely by communicating with a Window based PC and also to monitor whether exact voltage is output or not. These things are impossible in an analog control. In this paper, a simple buck converter controlled by DSP(TMS320C31) is implemented. This converter outputs 0V to 5V from 15V input voltage and is controlled by a PD algorithm using DSP. Finally the response characteristics of a step reference voltage and in a steady state are analyzed to verify the usefulness of this digital controlled converter.

• Proceedings of the KIEE Conference
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• 1997.07f
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• pp.2033-2036
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• 1997

In this paper, we proposed a novel current-fed DC-DC converter with multi-output. It has two winding reactor in series with the input source of the converter. By using the 2nd winding recycling the energy stored in the reactor to the input, the double-outputs DC-DC converter can be created, which makes it a good choice for a multi-output power supply with more outputs and has savings in cost and space. The steady state and dynamic characteristics of the converter are analyzed in detail by using the state space averaging method. It is found that the maximum value of $V_{o2}$ exists in the 2nd output and also during the MOSFET off period, the energy stored in the magnetizing inductance is reset through auxiliary winding $N_3$, so the duty cycle is restricted to 50%. Theoretical and experimental results were taken from the converter rated at switching frequency 50kHz. input voltage 50V. output voltage 5V. 12V and output power 65W. As a result, both results were well consistent. Therefore, it is varified the validity of the proposed converter in this paper.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.2
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• pp.47-52
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• 2017

In this paper, CMOS SAR A/D converter 1.8V supply for the design of an A/D converter having an middle speed for the biological signal processing was designed. This paper proposes design of a 10-bit SAR Analog to Digital Converter improving linearity driven by MSB node of C-DAC array divided into 4 equal parts. It enhances linearity property, by retaining the analog input signal charging time at MSB node. Because MSB node samples analog input, it enhances resolution through getting initial input signal precisely. By using split capacitor on C-DAC array, it reduced chip size and power dissipation. The Proposed SAR A/D Converter is fabricated in 0.18um CMOS and measured 7.5 bits of ENOB at sampling frequency 4MS/s and power supply of 1.8V. It occupies a core area of $850{\times}650um^2$ and consumes 123.105uW. Therefore it results in 170.016fJ/step of FOM(Figure of Merit).

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.8
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• pp.31-40
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• 2009

This paper presents a design of a high performance DC-DC boost converter as a power module for SOC designs. It applied to this chip that reduced inductor and capacitor for integrating on a chip, and it operates with a switching frequency of 100MHz. It has reliability and stability in high switching frequency. The controller of DC-DC boost converter is designed by voltage-mode control method and compensated properly. The designed DC-DC converter is fabricated with the 0.18${\mu}m$ standard CMOS technology with a thick-gate oxide option. The overall die size is 8.14$mm^2$, and controller size is 1.15$mm^2$. The converter has the maximum efficiency over 76% for the output voltage of 4V and load current larger 300mA. The load regulation is 0.012% (0.5mV) for the load current change of 100mA.

• Resources Recycling
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• v.22 no.4
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• pp.38-45
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• 2013

The porous ceramic beads using mine tailing were prepared and applied to catalytic converter for NOx/SOx removal. Catalytic support was used synthesized mesoporous silica (SBA-15) which coated on surface. Internal structure for porous ceramic beads was composed of three-dimensional network structure and porosity was about 80%. In addition, the specific surface area for mesoporous silica(SBA-15) coated on converter was significantly increased 55 $m^2/g$ compared with 0.8 $m^2/g$ before coating. NOx/SOx removal experiment was performed using $V_2O_5$ and $V_2O_5$/CuO converter. NOx conversion ratio for $V_2O_5$/CuO converter was approximately increased 10% compared to $V_2O_5$ converter. In addition, catalytic converter of $V_2O_5$/CuO was shown to remove 95% of NOx and 90% of SOx at reaction temperature of $350^{\circ}C$, space velocity of 10000 $h^{-1}$ and $O_2$ concentrations of 5%, respectively.

• Journal of the Korean Institute of Telematics and Electronics T
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• v.36T no.3
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• pp.56-63
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• 1999

In this paper, we realize the active PFC(Power Factor Correction) system of BF (Boost Forward) converter with PWM-PFM control technique to control DC output voltage, and to control the input current with sinusoidal wave synchronized by the converter and inverter using power switching element, FET and IGBT. The control circuit of the suggested Boost converter is implemented with a microprocessor 80C196. After making the ratio of output voltage to current as 50V/1A and the duty ratio greater than 0.5. When input voltage is 30V and boost inductance is 1.1mH. We control the voltage changing rate according to the variation of load resistance using a PWM-PFM control technique. And finally we prove experimentally. PF can be improved up to 0.96 using the current shaping technique.

• Journal of IKEEE
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• v.22 no.4
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• pp.1012-1018
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• 2018

In this paper, CMOS SAR (Successive Approximation Register) A/D converter with 1.8V supply voltage is designed for IoT sensor processing. This paper proposes design of a 12-bit SAR A/D converter with two A / D converters in parallel to improve the sampling rate. A/D converter1 of the two A/D converters determines all the 12-bit bits, and another A/D converter2 uses the upper six bits of the other A/D converters to minimize power consumption and switching energy. Since the second A/D converter2 does not determine the upper 6 bits, the control circuits and SAR Logic are not needed and the area is minimized. In addition, the switching energy increases as the large capacitor capacity and the large voltage change in the C-DAC, and the second A/D converter does not determine the upper 6 bits, thereby reducing the switching energy. It is also possible to reduce the process variation in the C-DAC by proposed structure by the split capacitor capacity in the C-DAC equals the unit capacitor capacity. The proposed SAR A/D converter was designed using 0.18um CMOS process, and the supply voltage of 1.8V, the conversion speed of 10MS/s, and the Effective Number of Bit (ENOB) of 10.2 bits were measured. The area of core block is $600{\times}900um^2$, the total power consumption is $79.58{\mu}W$, and the FOM (Figure of Merit) is 6.716fJ / step.

• Proceedings of the KIPE Conference
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• 2003.07a
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• pp.62-65
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• 2003

We considered of the efficiency for the Buck+Half bridge converter This converter has advantages of applications for a low output voltage, a high output current and a wide input voltage. Developed the Buck converter ratings and the Half Bridge converter ratings are 36$\~$72V Input and 22V/5A output, 19$\~$24v input and 3.3V/30A output, respectively. Buck converter is operated with zero voltage switching process to reduce the switching losses. The 80.1 $\~$97.6$\%$ of the efficiency is measured at 18.4 $\mu$H output filter inductance of Buck convertor. In Half Bridge convertor, the 86$\~$96.4$\%$ of the efficiency is measured at 100kHz switching frequency with PQI core.

• Journal of Power Electronics
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• v.12 no.3
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• pp.418-428
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• 2012

It is very important to improve the overall efficiency of systems with a source of power that has low-voltage high-current terminal characteristics such as fuel cells. A resonant converter is required for high efficiency systems. However, the peak value of the switches current is large in a resonant converter. This peak current requires a large number of switches and results in system failures. In this paper, an analysis and experiments of a resonant isolation push-pull converter are performed. A switching loss analysis is performed in order to compare losses between a resonant push pull converter and a hard switching push-pull converter. Specially, the conduction loss is studied based on the ratio between the resonant frequency and the switching frequency. In addition, a method for improving the efficiency is implemented with conventional HF insolation converters.

• Journal of the Korean Institute of Telematics and Electronics T
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• v.35T no.1
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• pp.48-58
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• 1998

For the purpose of designing novel capacitance pressure sensor, several effects on sensitivity such as parasitic capacitance effects, temperature/thermal drift and leakage current have to be eleiminated. This paper proposed the experimental studies on frequency compensation method by electronic circuit technique, C-V converting method with switched capacitor and C-F converting method with schmitt trigger circuit. The third interface circuit by frequency compensation method is composed to eliminate the drift and leakage component by comparision sensing frequency with reference frequency. The signal transmission is realized by digital signal to minimize the influence of noise and high resolution is obtained by means of increasing the number of digital bits. In the fabricated high performance C-V interface, the offset voltage was not appeared, and in case of voltage source, 4.0V, feed back capacitance, 10㎊, the pressure, 0~10 ㎪, the sensitivity of C-V converter is 28 ㎷/㎪.V, the temperature drift characteristic, 0.051 %F.S./$^{\circ}C$ and C-F converter shows -6.6 Hz/pa, 0.078 %F.S./$^{\circ}C$ respectively, relatively good ones.