• Journal of Microbiology and Biotechnology
• /
• v.24 no.11
• /
• pp.1525-1535
• /
• 2014

The xynC gene, which encodes high molecular weight xylanase from Paenibacillus sp. DG-22, was cloned and expressed in Escherichia coli, and its nucleotide sequence was determined. The xynC gene comprised a 4,419bp open reading frame encoding 1,472 amino acid residues, including a 27 amino acid signal sequence. Sequence analysis indicated that XynC is a multidomain enzyme composed of two family 4_9 carbohydrate-binding modules (CBMs), a catalytic domain of family 10 glycosyl hydrolases, a family 9 CBM, and three S-layer homologous domains. Recombinant XynC was purified to homogeneity by heat treatment, followed by Avicel affinity chromatography. SDS-PAGE and zymogram analysis of the purified enzyme identified three active truncated xylanase species. Protein sequencing of these truncated proteins showed that all had identical N-terminal sequences. In the protein characterization, recombinant XynC exhibited optimal activity at pH 6.5 and $65^{\circ}C$ and remained stable at neutral to alkaline pH (pH 6.0-10.0). The xylanase activity of recombinant XynC was strongly inhibited by 1 mM $Cu^{2+}$ and $Hg^{2+}$, whereas it was noticeably enhanced by 10 mM dithiothreitol. The enzyme exhibited strong activity towards xylans, including beechwood xylan and arabinoxylan, whereas it showed no cellulase activity. The hydrolyzed product patterns of birchwood xylan and xylooligosaccharides by thin-layer chromatography confirmed XynC as an endoxylanase.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.26 no.12C
• /
• pp.249-254
• /
• 2001

A receiver ASIC for fiber optic modules of STM-1 optical communication has been fabricated with 0.65 $\mu\textrm{m}$ CMOS technology. The ASIC has a limit amplifier circuit for the 155.52 Mbps data reshaping, and a clock extraction circuit for the 155.52 MHz clock recovery. The ASIC has an acquisition aid and LOS monitoring circuit for properly operation with near 155.52 MHz clock frequency in case of the data loss due to transmission line open or data transfer fail. Measured results show that the circuit reshapes data from 5 mV to 1 V wide range of input voltage condition, add it recovers system clock with stable on any condition.

• Journal of the Korean Mathematical Society
• /
• v.41 no.1
• /
• pp.209-229
• /
• 2004

Let $\Sigma_{$\mid$\alpha$\mid$=m}\;s_{\alpha}z^{\alpha},\;z\;{\in}\;{\mathbb{C}}^n$ be a unimodular m-homogeneous polynomial in n variables (i.e. $$\mid$s_{\alpha}$\mid$\;=\;1$ for all multi indices $\alpha$), and let $R\;{\subset}\;{\mathbb{C}}^n$ be a (bounded complete) Reinhardt domain. We give lower bounds for the maximum modules $sup_{z\;{\in}\;R\;$\mid$\Sigma_{$\mid$\alpha$\mid$=m}\;s_{\alpha}z^{\alpha}$\mid$$, and upper estimates for the average of these maximum moduli taken over all possible m-homogeneous Bernoulli polynomials (i.e. $s_{\alpha}\;=\;{\pm}1$ for all multi indices $\alpha$). Examples show that for a fixed degree m our estimates, for rather large classes of domains R, are asymptotically optimal in the dimension n.

• The Transactions of the Korea Information Processing Society
• /
• v.4 no.11
• /
• pp.2914-2922
• /
• 1997

For FA (factory automation) and ATE (automatic test equipment) in the industrial area, the standard bus needs to increase the system performance of multiprocessor environment. VME(versa module european package format) bus is appropriated to the standard bus but has features of small package and low board density. Beside, the density of board and semiconductor have grown to become significant issues that affect development time, project cost and field diagnostics. To fit this trend, in this paper, we composed Revision C.1 (IEEE std. P1014-1987) of the integrated environment for the main function such as arbitration, interrupt and interface between, VMEbus and several control modules Also the designed, VME system controller is implemented on FPGA that can be located even into slot 1. The control and function modules are coded with VHDL mid-fixed description method and then those operations are verified by simulation. As a result of experiment, we confirmed the most important that is the operation of Bus timer about Bus error signal should occur within $56{\mu}m$, and both control and function modules have the reciprocal operation correctly. Thus, the constructed VHDL library will be able to apply the system based VMEbus and ASIC design.

• Journal of Ocean Engineering and Technology
• /
• v.21 no.3 s.76
• /
• pp.46-51
• /
• 2007

A multi-purpose environmental monitoring system has been developed as a commercially available standard using the technique of hetero-core spliced fiber optic sensors, for the purposes of monitoring large-scale structures and preserving natural environments. The monitoring system has been tested and evaluated in a possible outdoor condition, in view of the full-scale operation at actual sites to be monitored. Additionally, the developed system in this work conveniently provides us with various options of sensor modules intended for monitoring such physical quantities as displacement, distortion, pressure, binary states, and liquid adhesion. Two channels of optical fiber line were monitored in each channel, three displacement sensor modules were connected in series, in order to examine the performance to a pseudo-cracking experiment in the outdoor situation and to clarify temperature influences an the system, in terms of the coupling of optical connectors and the OTDR stability. The results from the pseudo-cracking experiment agreed with the actual cracks, by means of calculation, based an the detected displacement values and their geometrical arrangement of the used sensor modules. The temperature change, ranging from 10 to $20^{\circ}C$ resulting from the 10-days free running operation, was found to influence the system stability of ${\pm}10{\mu}m$, primarily due to the coupling instability of the used optical connectors. It was found that fusion splicing, rather than the use of connectors, reduced the fluctuation dawn to ${\pm}2{\mu}m$. The specification and performance of various option modules have been demonstrated to show the capability of inspecting various physical quantities by use of the single system, which would be suitable for multi-purpose environmental monitoring.

• Communications of the Korean Mathematical Society
• /
• v.38 no.3
• /
• pp.733-740
• /
• 2023

Let R be a commutative ring and M be an R-module. The dimension graph of M, denoted by DG(M), is a simple undirected graph whose vertex set is Z(M) ⧵ Ann(M) and two distinct vertices x and y are adjacent if and only if dim M/(x, y)M = min{dim M/xM, dim M/yM}. It is shown that DG(M) is a disconnected graph if and only if (i) Ass(M) = {𝖕, 𝖖}, Z(M) = 𝖕 ∪ 𝖖 and Ann(M) = 𝖕 ∩ 𝖖. (ii) dim M = dim R/𝖕 = dim R/𝖖. (iii) dim M/xM = dim M for all x ∈ Z(M) ⧵ Ann(M). Furthermore, it is shown that diam(DG(M)) ≤ 2 and gr(DG(M)) = 3, whenever M is Noetherian with |Z(M) ⧵ Ann(M)| ≥ 3 and DG(M) is a connected graph.

• Journal of the Microelectronics and Packaging Society
• /
• v.7 no.1
• /
• pp.13-18
• /
• 2000

Low temperature co-fired ceramics on metal (LTCC-M) is efficient for embedding passive components with good tolerance in a module due to the dimensional stability in x and y directions by the constraint of metal core during the firing. In addition, the radiation noise can be reduced by metal core. In this paper, embedded passive components were introduced and a power amplifier module (PAM) fabricated by using the passive components was explained. The embedded passive components in test patters showed the tolerance of 10~20% and the good repeatability in tolerance of embedded passives was maintained in module fabrication. The shortened traces in multi chip modules (MCMs) make the signal delay time decreased and the embedded passives simplify the packaging processes owing to the less solder points, which enhance the electrical performance and increase the reliability of the modules. The LTCC-M technology is one of the promising candidates for RF application and is expected to expand its applications to power and high performance devices.

• Proceedings of the KOSOMBE Conference
• /
• v.1996 no.05
• /
• pp.315-319
• /
• 1996

We have developed a prototype patient monitoring system including module-based bedside units, interbed network, and central stations. A bedside unit consists of a color monitor and a main CPU unit with peripherals including a module controller. It can also include up to 3 module cases and 21 different modules. In addition to the 3-channel recorder module, six different physiological parameters of ECG, respiration, invasive blood pressure, noninvasive blood pressure, body temperature, and arterial pulse oximetry with plethysmogaph are provided as parameter modules. Modules and a module controller communicate with up to 1Mbps data rate through an intrabed network based on RS-485 and HDLC protocol. Bedside units can display up to 12 channels of waveforms with any related numeric informations simultaneously. At the same time, it communicates with other bedside units and central stations through interbed network based on 10Mbps Ethernet and TCP/IP protocol. Software far bedside units and central stations fully utilizes gaphical user interface techniques and all functions are controlled by a rotate/push button on bedside unit and a mouse on central station. The entire system satisfies the requirements of AAMI and ANSI standards in terms of electrical safety and performances. In order to accommodate more advanced data management capabilities such as 24-hour full disclosure, we are developing a relational database server dedicated to the patient monitoring system. We are also developing a clinical workstation with which physicians can review and examine the data from patients through various kinds of computer networks far diagnosis and report generation. Portable bedside units with LCD display and wired or wireless data communication capability will be developed in the near future. New parameter modules including cardiac output, capnograph, and other gas analysis functions will be added.

• Journal of the Institute of Electronics Engineers of Korea SC
• /
• v.40 no.6
• /
• pp.24-30
• /
• 2003

This study focuses on the arithmetical methodology and hardware implementation of low system-complexity A $B^2$＋C operator over GF(2$^{m}$ ) using the irreducible AOP of degree m. The proposed parallel-in parallel-out operator is composed of CS, PP, and MS modules, each can be established using the array structure of AND and XOR gates. The proposed multiplier is composed of (m＋1)$^2$ 2-input AND gates and (m＋1)(m＋2) 2-input XOR gates. And the minimum propagation delay is $T_{A}$ ＋(1＋$\ulcorner$lo $g_2$$^{m}$ $\lrcorner$) $T_{x}$ . Comparison result of the related A $B^2$＋C operators of GF(2$^{m}$ ) are shown by table, It reveals that our operator involve more lower circuit complexity and shorter propagation delay then the others. Moreover, the interconnections of the out operators is very simple, regular, and therefore well-suited for VLSI implementation.

• Bulletin of the Korean Mathematical Society
• /
• v.43 no.4
• /
• pp.723-735
• /
• 2006

In [2] it was shown that a 1-generator quasi-cyclic code C of length n = ml of index l over $\mathbb{Z}_4$ is free if C is generated by a polynomial which divides $X^m-1$. In this paper, we prove that a necessary and sufficient condition for a cyclic code over $\mathbb{Z}_pk$ of length m to be free is that it is generated by a polynomial which divides $X^m-1$. We also show that this can be extended to finite local rings with a principal maximal ideal.