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Low System Complexity Bit-Parallel Architecture for Computing $AB^2+C$ in a Class of Finite Fields $GF(2^m)$  

변기령 (가톨릭대학교 정보통신전자공학부)
김흥수 (인하대학교 전자공학과)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SC / v.40, no.6, 2003 , pp. 24-30 More about this Journal
Abstract
This study focuses on the arithmetical methodology and hardware implementation of low system-complexity A $B^2$＋C operator over GF(2$^{m}$ ) using the irreducible AOP of degree m. The proposed parallel-in parallel-out operator is composed of CS, PP, and MS modules, each can be established using the array structure of AND and XOR gates. The proposed multiplier is composed of (m＋1)$^2$ 2-input AND gates and (m＋1)(m＋2) 2-input XOR gates. And the minimum propagation delay is $T_{A}$ ＋(1＋$\ulcorner$lo $g_2$$^{m}$ $\lrcorner$) $T_{x}$ . Comparison result of the related A $B^2$＋C operators of GF(2$^{m}$ ) are shown by table, It reveals that our operator involve more lower circuit complexity and shorter propagation delay then the others. Moreover, the interconnections of the out operators is very simple, regular, and therefore well-suited for VLSI implementation.
Keywords
finite field; all one polynomial; standard basis; $GF(2^m)$ multiplier; power-sum;
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