• IT SoC Magazine
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• s.19
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• pp.24-28
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• 2007

올해 44회를 맞이한 DAC(Design Automation Conference)는 6월 4일부터 8일까지 5일간 캘리포니아 샌디에고에서 개최되었다. 이번 DAC에도 샌프란시스코에서 열렸던 43회 DAC와 마찬가지로 인텔, IBM, ARM, Sun Microsystems 등 첨단 SoC/IP 설계회사와 Cadence, Synopsys 등 EDA 개발회사, 그리고 TSMC, UMC 등 유수의 파운드리회사들이 참가하였다. 전시회 참여업체는 약 250여개로 예년보다 약간 증가하였고 총 참관객수는 11,000여명으로 다소 줄어들었다. 하지만 국내 참여업체 관계자들은 참관객들의 질적인 수준이 작년 DAC보다 더 높아 제품을 홍보하고 관련 업계 사람들과 정보를 교환하기에 더없이 좋은 기회였다고 평가했다. 또한 이번 DAC 컨퍼런스는 총 10개 트랙, 53개의 세션들이 진행되었으며 약 161개의 논문이 발표되어 매우 역동적인 기술교류가 이루어졌다. 여기에서는 44th DAC의 주요 이슈와 전시회에 참여하였던 국내 SoC업체들의 제품에 대해 살펴 보고자한다.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.2
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• pp.47-52
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• 2017

In this paper, CMOS SAR A/D converter 1.8V supply for the design of an A/D converter having an middle speed for the biological signal processing was designed. This paper proposes design of a 10-bit SAR Analog to Digital Converter improving linearity driven by MSB node of C-DAC array divided into 4 equal parts. It enhances linearity property, by retaining the analog input signal charging time at MSB node. Because MSB node samples analog input, it enhances resolution through getting initial input signal precisely. By using split capacitor on C-DAC array, it reduced chip size and power dissipation. The Proposed SAR A/D Converter is fabricated in 0.18um CMOS and measured 7.5 bits of ENOB at sampling frequency 4MS/s and power supply of 1.8V. It occupies a core area of $850{\times}650um^2$ and consumes 123.105uW. Therefore it results in 170.016fJ/step of FOM(Figure of Merit).

• The Journal of the Petrological Society of Korea
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• v.5 no.2
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• pp.129-134
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• 1996

Possibile phase transitions of graphite have been examined experimentally using piston cylinder and DAC with synchrotron radiation. The graphite-forming processes in high pressure and low temperature conditions and the phase change under super high pressure were studied in the conditions of 0.7 Gpa and 270-$360^{\circ}C$ in piston cylinder and under 39.6 Gpa in DAC. In the piston cylinder experiment using LiCO3as a catalyzer, we could synthesize disordered graphites whose TGD values change progressively form 9 to 53. It was known that the temperature of graphitization in 0.7 Gpa is between 270-$300^{\circ}C$. Numerous unknown XRD peaks were observed in the super high-pressure experiment. However, it is difficult to pick up a new peak of a hexagonal diamond phase. Application of the different high pressure apparatus as well as a peculiar X-ray source and various graphite specimen would be useful for super high-pressure experiment, and more detailed works are needed to characterize the unknown phase(s) observed in this study.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.4
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• pp.50-59
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• 1998

This paper describes a 3.3V 8bit CMOS digital to analog converter (DAC) with two state current cell metrix architecture which consists of a 4 MSB and a 4 LSB current matrix stage. The symmetric two stage current cell matrix architecture allow the designed DAC to reduce hot only a complexity of decoding logics, but also a number of wider swing cascode curent mirros. The designed DAC with an active chip area of 0.8 mm$_{2}$ is fabricated by a 0.8 .mu.m CMOS n-well standard digital process. The experimental data shows that the rise/fall time, the settling time, and INL/DNL are6ns, 15ns, and a less than .+-.0.8/.+-.0.75 LB, respectively. The designed DAC is fully operational for the power supply down to 2.0V, such that the DAC is suitable for a low voltage and a low power system application. The power dissipation of the DAC with a single power supply of 3.3V is measured to be 34.5mW.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.6
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• pp.28-36
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• 1997

In this work, a highly linear video-speed CMOS current-mode digital-to-analog converter (DAC) is proposed. A newswitching scheme for the current cell matrix of the DAC simultaneously reduces graded and symmetrical errors to improve integral nonlinearities (INL). The proposed DAC is designed to operate at any supply voltage between 3V and 5V, and minimizes the glitch energy of analog outputs with degliching circuits developed in this work. The prototype dAC was implemented in a LG 0.8um n-well single-poly double-metal CMOS technology. Experimental results show that the differential and integral nonlinearities are less than .+-. LSB and .+-.0.8LSB respectively. The DAC dissipates 75mW at a 3V single power supply and occupies a chip area of 2.4 mm * 2.9mm.

• IMMUNE NETWORK
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• v.12 no.2
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• pp.58-65
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• 2012

Background: A cell line with transfected Wilms' tumor protein 1 (WT1) is has been used for the preclinical evaluation of novel treatment strategies of WT1 immunotherapy for leukemia due to the lack of appropriate murine leukemia cell line with endogenous WT1. However, silencing of the transgene occurs. Regarding the effects of hypomethylating agents (HMAs) on reactivation of silenced genes, HMAs are considered to be immune enhancers. Methods: We treated murine WT1- transfected C1498 (mWT1-C1498) with increasing doses of decitabine (DAC) and azacitidine (AZA) to analyze their effects on transgene reactivation. Results: DAC and AZA decreased the number of viable cells in a dose- or time-dependent manner. Quantification of WT1 mRNA level was analyzed by real-time polymerase chain reaction after mWT1-C1498 treated with increasing dose of HMA. DAC treatment for 48 h induced 1.4-, 14.6-, and 15.5-fold increment of WT1 mRNA level, compared to untreated sample, at 0.1, 1, and $10{\mu}M$, respectively. Further increment of WT1 expression in the presence of 1 and $10{\mu}M$ DAC was evident at 72 h. AZA treatment also induced up-regulation of mRNA, but not to the same degree as with DAC treatment. The correlation between the incremental increases in WT1 mRNA by DAC was confirmed by Western blot and concomitant down-regulation of WT1 promoter methylation was revealed. Conclusion: The in vitro data show that HMA can induce reactivation of WT1 transgene and that DAC is more effective, at least in mWT1-C1498 cells, which suggests that the combination of DAC and mWT1-C1498 can be used for the development of the experimental model of HMA-combined WT1 immunotherapy targeting leukemia.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.7
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• pp.1543-1551
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• 2011

Dithering scheme has been widely used to improve the resolution of DCO(Digitally Controlled Oscillator) in conventional ADPLLs(All Digital Phase Locked Loop). In this paper a new resolution improvement scheme is proposed where a simple DAC(Digital-to-Analog Converter) is employed to overcome the problems of dithering scheme. The frequencies are controled by varactors in coarse, fine, and DAC bank. The DAC bank consists of an inversion mode NMOS varactor. The other varactor banks consist of PMOS varactors. Each varactor bank is controlled by 8bit digital signal. The proposed DCO has been designed in a $0.13{\mu}m$ CMOS process. Measurement results shows that the designed DCO oscillates in 2.8GHz~3.5GHz and has a frequency tuning range of 660MHz and a resolution of 73Hz at 2.8GHz band. The designed DCO exhibits a phase noise of -119dBc/Hz at lMHz frequency offset. The DCO core consumes 4.2mA from l.2V supply. The chip area is $1.3mm{\times}1.3mm$ including pads.

• Journal of IKEEE
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• v.22 no.4
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• pp.1012-1018
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• 2018

In this paper, CMOS SAR (Successive Approximation Register) A/D converter with 1.8V supply voltage is designed for IoT sensor processing. This paper proposes design of a 12-bit SAR A/D converter with two A / D converters in parallel to improve the sampling rate. A/D converter1 of the two A/D converters determines all the 12-bit bits, and another A/D converter2 uses the upper six bits of the other A/D converters to minimize power consumption and switching energy. Since the second A/D converter2 does not determine the upper 6 bits, the control circuits and SAR Logic are not needed and the area is minimized. In addition, the switching energy increases as the large capacitor capacity and the large voltage change in the C-DAC, and the second A/D converter does not determine the upper 6 bits, thereby reducing the switching energy. It is also possible to reduce the process variation in the C-DAC by proposed structure by the split capacitor capacity in the C-DAC equals the unit capacitor capacity. The proposed SAR A/D converter was designed using 0.18um CMOS process, and the supply voltage of 1.8V, the conversion speed of 10MS/s, and the Effective Number of Bit (ENOB) of 10.2 bits were measured. The area of core block is $600{\times}900um^2$, the total power consumption is $79.58{\mu}W$, and the FOM (Figure of Merit) is 6.716fJ / step.

• Microbiology and Biotechnology Letters
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• v.15 no.6
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• pp.375-380
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• 1987

D-$\alpha$-Amino-$\varepsilon$-carpolactam racemase (EC 5.1.1) and L-$\alpha$-amino-$\varepsilon$-caprolactam hydrolase (EC 3.5.2) were fractionated from cell-free extracts of Alcaligenes eutrophus A52 using ammonium sulfate precipitation and DEAE-cellulose ion exchange chromatography. It was made sure that D-$\alpha$-amino-$\varepsilon$-caprolactam was converted to L-$\alpha$-amino-$\varepsilon$-caprolactam by racemase, and then hydrolyzed into L-lysine by hydrolase in Alcaligenes eutrophus A52. For the conversion of D-$\alpha$-amino-$\varepsilon$-caprolactam into L-lysine by cell-free extracts of Alcaligenes eutrophus A52, the optimum temperature and pH were 6$0^{\circ}C$ and 8.5 respectively. The results showed that 0.5% D-$\alpha$-amino-$\varepsilon$-caprolactam was converted to L-lysine at 55$^{\circ}C$ for 10 hr with a conversion rate of 98% by cell-free extracts containing 3.1mg of protein.

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.1
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• pp.23-32
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• 2011

A 40 fJ/c-s, 1 V, 10-bit SAR ADC is presented for energy constrained wearable body sensor network application. The proposed 10-bit dual sampling capacitive DAC topology reduces switching energy by 62% compared with 10-bit conventional SAR ADC. Also, it is more robust to capacitor mismatch than the conventional architecture due to its cancelling effect of each capacitive DAC. The proposed SAR ADC is fabricated in 0.18 ${\mu}m$ 1P6M CMOS technology and occupies 1.17 $mm^2$ including pads. It dissipates only 1.1 ${\mu}W$ with 1 V supply voltage while operating at 100 kS/s.