• Journal of the Semiconductor & Display Technology
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• v.21 no.4
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• pp.27-32
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• 2022

RISC-V is an open instruction set architecture (ISA) developed in 2010 at UC Berkeley, and active research is being conducted as a processor to compete with ARM. In this paper, we propose an SoC system including an RV32I ISA-based 32-bit 5-stage pipeline processor and AHB bus master. The proposed RISC-V processor supports 37 instructions, excluding FENCE, ECALL, and EBREAK instructions, out of a total of 40 instructions based on RV32I ISA. In addition, the RISC-V processor can be connected to peripheral devices such as BRAM, UART, and TIMER using the AHB-lite bus protocol through the proposed AHB bus master. The proposed SoC system was implemented in Arty A7-35T FPGA with 1,959 LUTs and 1,982 flip-flops. Furthermore, the proposed hardware has a maximum operating frequency of 50 MHz. In the Dhrystone benchmark, the proposed processor performance was confirmed to be 0.48 DMIPS.

• Journal of the military operations research society of Korea
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• v.11 no.1
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• pp.55-78
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• 1985

This thesis provides the implementation of a simulation model for a particular Local Area Network (LAN), employs carrier sense multiple access (CSMA) bus architecture, which implements functions of the Stock Point Logistics Integrated Communication Environment (SPLICE). First, specifications of the model are identified based on the given functional specification and operating system design. Then the approach taken for modeling and programming in GPSS is discussed. Finally, the program and results of the simulation run are provided.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.38 no.6
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• pp.620-628
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• 2010

Small satellites can be used for various space research and scientific or educational purposes due to advantages in small size, low-cost, and rapid development. Small Satellites have many advantages of application to Responsive Space. Compared to traditional larger satellites, however, Small satellites have many constraints due to limitations in size. Therefore, it is difficult to expect high performance. To approach maximum capability with minimal size, weight, and cost, standard modular platform of Small satellites is necessary. Modularity supports plug-and-play architecture. The result is Small satellites that can be combined quickly and reliably using plug-and-play mechanisms. For communication between modules, standard bus interface is needed. Controller Area Network(CAN) protocol is considered optimum data bus for modular Small satellite. CAN can be applied to data communication with high reliability. Hence, design optimization and simplification can also be expected. For ease of assembly and integration, modular design can be considered. This paper proposes development method for standardized modular Small satellites, and describes design of data interface based on CAN and a method of testing for modularity.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.10a
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• pp.281-284
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• 2008

This paper describes ASIC design of multimedia SoC Platform. The implemented Platform consists of 32-bit OpenRISC1200 Microprocessor, WISHBONE on-chip bus, VGA Controller, Debug Interface, SRAM Interface and UART. The 32-bit OpenRISC1200 processor has 5 stage pipeline and Harvard architecture with separated instruction/data bus. The VGA Controller can display RCB data on a CRT or LCD monitor. The Debug Interface supports a debugging function for the Platform. The SRAM Interface supports 18-bit address bus and 32-bit data bus. The UART provides RS232 protocol, which supports serial communication function. The Platform is design and verified on a Xilinx VERTEX-4 XC4VLX80 FPGA board. Test code is generated by a cross compiler' and JTAG utility software and gdb are used to download the test code to the FPGA board through parallel cable. Finally, the Platform is implemented into a single ASIC chip using Chatered 0.18um process and it can operate at 100MHz clock frequency.

• The Journal of the Korea Contents Association
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• v.7 no.11
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• pp.84-93
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• 2007

This paper presents a methodology that accelerates estimating the system-level power consumption for on-chip bus of SoC platforms. The proposed power modeling can estimate the power consumption according to the change of a target SoC system. The proposed model comprises two parts: the one is power estimation of bus logics reflecting the architecture of the bus such as the number of bus layers, the other is to estimate the power consumed by the bus lines during data transmission. We designed the target multimedia SoC system, MPEG encoder as an example and evaluated power consumption using this model. The simulation result shows that the accuracy of the proposed model is over 92%. Thus, the proposed power model can be used to design of a high-performance/low-power multimedia SoC.

• Journal of the Korea Institute of Military Science and Technology
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• v.14 no.4
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• pp.598-606
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• 2011

The importance of avionics systems has increased to a significant level in modern aircraft development. Modern avionics system is a complex integrated system of state-of-art hardware and software technology. Specifying the avionics system architecture is the most important task throughout the avionics system design process. This paper reviews modern avionics system architectures and proposes an effective avionics architecture suitable for modern attack helicopters.

• Proceedings of the KIEE Conference
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• 2002.07d
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• pp.2755-2757
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• 2002

In this paper, we propose a now architecture for hardware implementation of digital neural network. By adopting flexible ladder-style bus and internal connection network into traditional SIMD-type digital neural network architecture, the proposed architecture enables fast processing that is based on parallelism, while does not abandon the flexibility and extensibility of the traditional approach. In the proposed architecture, users can change the network topology by setting configuration registers. Such reconfigurability on hardware allows enough usability like software simulation. We implement the proposed design on real FPGA, and configure the chip to multi-layer perceptron with back propagation for alphabet recognition problem. Performance comparison with its software counterpart shows its value in the aspect of performance and flexibility.

• Journal of KIISE:Computer Systems and Theory
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• v.29 no.2
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• pp.105-115
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• 2002

Since NUMA architecture has to access remote memory an interconnection network determines the performance of CC-NUMA system Bus which has been used as a popular interconnection network has many limits to build a large-scale system because of the limited physical scalabilty and bandwidth Dual ring interconnection network composed of high speed point-to-point links is made up for resolving the defects of the bus for large-scale system But it also has a problem that the response latency is rapidly increased when many node are attached to snooping based CC-NUMA system with dual ring In this paper we propose a chordal ring architecture in order to overcome the problem of the dual ring on snooping based CC-NUMA system and design and efficient link controller adopted to this architecture. We also analyze the effects of chordal ring architecture on the system performance and the response latency by using probability driven simulator.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.1
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• pp.107-112
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• 2012

In this contribution, we designed a general purpose input/output (GPIO) suitable for embedded systems, especially for Bluetooth baseband. Proposed architecture is compatible for the APB bus in AMBA bus architecture. General purpose I/O should be used as multi-functional and versatile interrupt sources. We considered the edge-sensitive mode as well as the level-sensitive mode for acquiring the interrupt sources. Also, we provided an option to select the operation polarity for flexible application to the embedded systems. The designed GPIO module was automatically synthesized, placed, and routed. The proposed GPIO was implemented through the Altera FPGA and well operated at 25MHz clock frequency.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.05a
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• pp.895-898
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• 2009

In this contribution, we designed a general purpose input/output (GPIO) suitable for embedded systems, especially for Bluetooth baseband. Proposed architecture is compatible for the APB bus in AMBA bus architecture. General purpose I/O should be used as multi-functional and versatile interrupt sources. We considered the edge-sensitive mode as well as the level-sensitive mode for acquiring the interrupt sources. Also, we provided an option to select the operation polarity for flexible application to the embedded systems. The designed GPIO module was automatically synthesized, placed, and routed. Implementation was performed through the Altera FPGA and well operated at 25MHz clock frequency.