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A Design and Implementation of 32-bit Five-Stage RISC-V Processor Using FPGA  

Jo, Sangun (Department of System Semiconductor Engineering, Sangmyung University)
Lee, Jonghwan (Department of System Semiconductor Engineering, Sangmyung University)
Kim, Yongwoo (Department of System Semiconductor Engineering, Sangmyung University)
Publication Information
Journal of the Semiconductor & Display Technology / v.21, no.4, 2022 , pp. 27-32 More about this Journal
Abstract
RISC-V is an open instruction set architecture (ISA) developed in 2010 at UC Berkeley, and active research is being conducted as a processor to compete with ARM. In this paper, we propose an SoC system including an RV32I ISA-based 32-bit 5-stage pipeline processor and AHB bus master. The proposed RISC-V processor supports 37 instructions, excluding FENCE, ECALL, and EBREAK instructions, out of a total of 40 instructions based on RV32I ISA. In addition, the RISC-V processor can be connected to peripheral devices such as BRAM, UART, and TIMER using the AHB-lite bus protocol through the proposed AHB bus master. The proposed SoC system was implemented in Arty A7-35T FPGA with 1,959 LUTs and 1,982 flip-flops. Furthermore, the proposed hardware has a maximum operating frequency of 50 MHz. In the Dhrystone benchmark, the proposed processor performance was confirmed to be 0.48 DMIPS.
Keywords
RISC-V; Processor; AMBA BUS; AHB-lite; FPGA;
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Times Cited By KSCI : 1  (Citation Analysis)
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