• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.9
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• pp.53-60
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• 1997

In this paper, an efficient BILBO(named EBILBO) is proposed for batch testing application when a BIST (built-in self test) circuit is implemented on ASIC. In a large and complex circuit, the proposed algorithm of batch testing has one pin-count that can easily control 4 test modes in the normal speed of circuit operation. For the implementation of the BIST cifcuit, the test patern needed is generated by PRTPG(pseudo-random test pattern generator) and the ouput is observed by proposed algorithm is easily modified, such as the modelling of test pattern genration, signature EBILBO area and performance of the implemented BIST are evaluated using ISCAS89 benchmark circuits. As a resutl, in a circuit above 600 gates, it is confirmed that test patterns are genrated flexibly about 500K as EBILBO area is 59%, and the range of fault coverage is from 88.3% to 100%. And the optimized operation frequency of EBILBO designed and the area are 50MHz and 150K respectively. On the BIST circit of the proposed batch testing, the test mode of EBILBO is able to execute as realtime that has te number of s$\^$+/n$\^$+/(2s/2p-1) clocks simultaneously with the normal mode of circuit operation. Also the proposed algorithm is made of the library with VHDL coding thus, it will be widely applied to DFT (design for testability) that satisfies the design and test field.

• Proceedings of the Korea Information Processing Society Conference
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• 2002.04a
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• pp.635-638
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• 2002

BIST(Built-In Self-Test)를 이용한 테스트 방식은 정상 동작 모드인 회로에 비해 테스트 모드에서 보다 많은 스위칭이 발생하고, 과도한 전력 소모에 의해 회로가 손상을 받을 수 있는 문제점을 갖고 있다. 본 논문은 test-per-clock BIST 구조에서 전력이 제한되어 있을 때 테스트 적용 시간과 총 에너지 소비를 최소화하기 위한 테스트 스케줄링 알고리즘을 제안한다. 제안된 방법은 테스트 세션을 구성함에 있어 각 세션에 포함되는 각 블록의 테스트 시작 시간을 동적으로 결정하여 기존의 알고리즘에 비하여 전력 소모와 전체 테스트 시간을 줄일 수 있다.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.1
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• pp.79-89
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• 2014

It has been an increase in consumers who want a high-capacity and fast speed by the newly diffused mobile device(Smart phones, Ultra books, Tablet PC). As a result, the demand for Flash Memory is constantly increasing. Flash Memory is separated by a NAND-type and NOR-type. NAND-type Flash Memory speed is slow, but price is cheaper than the NOR-type Flash Memory. For this reason, NAND-type Flash Memory is widely used in the mobile market. So Fault Detection is very important for Flash Memory Test. In this paper, Proposed PMBIST for Pattern Test of NAND-type Flash Memory improved Fault detection.

• Journal of Technologic Dentistry
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• v.16 no.1
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• pp.105-113
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• 1994

This study attempted to find out how much stress Dental Technicians of working in Dental Laboratory have built up in the midst of their daily lives are according to their sex, age, duration of work and their kinds of positions. After self-administered questionnaire were distributed by direct to 230 technicians samplely selected from dental laboratories in Seoul and Pusan of whom 163 technicians responded from october 1 through october 13, 1994. Analysis of the data was processed by t-test, $X^2$-test, ANOVA. This results are as follows. 1. Levels of Stress of the total 163 respondents by sex is not higher among male than female(p>.05). 2. Levels of stress - 36.2%(74 Dental technicians) of all Dental technicians were in stress on the whole and 9.2%(15 Dental technicians) of them were in a serious situation by accumulated stress. 3. Realization of stress - 10.1%(16 Dental technicians) of the dental technicians and 89.9%(143 Dental technicians) were found out to be in a dangerous sign or in a situation by accumulated stress. Further studies which a big size and a delicate method of measuring their general characteristics are needed.

• Journal of Institute of Control, Robotics and Systems
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• v.11 no.2
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• pp.160-166
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• 2005

In this paper, to overcome drawbacks of FLC a self tuning fuzzy sliding mode controller is proposed, which controls the position of excavator's attachment, which can be regarded as an ill-defined system. It is reported that fuzzy logic theory is especially useful in the control of ill-defined system. It is important in the design of a FLC to derive control rules in which the system's dynamic characteristics are taken into account. Control rules are usually established using trial and error methods. However, in the case where the dynamic characteristics vary with operating conditions, as in the operation of excavator attachment, it is difficult to find out control rules in which all the working condition parameters are considered. Experiments are carried out on a test bed which is built around a commercial Hyundai HX-60W hydraulic excavator. The experimental results show that both alleviation of chattering and performance are achieved. Fuzzy rules are easily obtained by using the proposed method and good performance in the following the desired trajectory is achieved. In summary, the proposed controller is very effective control method for the position control of the excavator's attachment.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.8
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• pp.9-16
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• 2004

For a System-on-a-Chip(SoC) comprised of multiple IP cores, test control techniques have been developed to perform the internal and external test efficiently relying on the various design for testability techniques such as scan and BIST(Built-In Self-Test). However the test area overhead is too expensive to guarantee diverse test link configurations. In this paper, at first we introduce a new flag based Wrapped Core Linking Module(WCLM) that enables systematic integration of IEEE 1149.1 TAP'd cores and P1500 wrapped cores. Then a simple test control technique, which can interconnect internal scan chains of different cores, is described with requiring least amount of area overhead compared with other state-of-art techniques. The design preserves compatibility with standards and scalability for hierarchical access.

• Structural Engineering and Mechanics
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• v.35 no.1
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• pp.37-52
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• 2010

Special-shape arch bridge for self-balance (SBSSAB) in Zhongshan City is a kind of new fashioned spatial combined arch bridge composed of inclined steel arch ribs, curved steel box girder and inclined suspenders, and the mechanical behavior of the SBSSAB is particularly complicated. The SBSSAB is aesthetic in appearance, and design of the SBSSAB is artful and particular. In order to roundly investigate the mechanical behavior of the SBSSAB, 3-D finite element models for spatial member and shell were established to analyze the mechanical properties of the SBSSAB using ANSYS. Finite element analyses were conducted under several main loading cases, moreover deformation and strain values for control section of the SBSSAB under several main loading cases were proposed. To ensure the safety and rationality for optimal design of the SBSSAB and also to verify the reliability of its design and calculation theories, the 1/10 scale model tests were carried out. The measured results include the load checking calculation, lane loading and crowd load, and dead load. A good agreement is achieved between the experimental and analytical results. Both experimental and analytical results have shown that the SBSSAB is in the elastic state under the planned test loads, which indicates that the SBSSAB has an adequate load-capacity. The calibrated finite-element model that reflects the as-built conditions can be used as a baseline for health monitoring and future maintenance of the SBSSAB.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.10
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• pp.2123-2135
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• 1997

In this paepr, we consider resistive shorts on drain-source, drain-gate, and gate-source as well as opens in MOSFETs included in typical memory cell of VLSI SRAM. Behavior of memeory is observed by analyzing voltage at storage nodes of memeory and IDDQ(quiescent power supply current) through PSPICE simulation. Using this behavioral analysis, an effective testing algorithm of complexity O(N) which can be applied to both functional testing and IDDQ testing simultaeously is proposed. Built-In Self Test(BIST) circuit which detects faults in memories and Built-In Current Sensor(BICS) which monitors the power supply bus for abnormalities in quescent current are developed and imprlemented to improve the quality and efficiency of testing. Implemented BIST and BICS circuits can detect locations of faults and defects in order to repair faulty memories.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.10a
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• pp.818-823
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• 2003

본 논문에서는 입력 매칭(input matching) BIST(Built-In Self-Test) 회로를 이용한 RF font end의 새로운 결함 검사방법을 제안한다. BIST 회로를 가진 RF front end는 1.8GHz LNA(Low Noise Amplifier: 저 잡음 증폭기)와 이중 대칭 구조의 Gilbert 셀 믹서로 구성되어 있으며, TSMC 0.25$\mu\textrm{m}$ CMOS 기술을 이용하여 설계되었다. catastrophic 결함 및 parametric 변동을 가진 RF front end와 결함을 갖지 않은 RF front end를 판별하기 위해 RF front end의 입력 전압 특성을 조사하였다. 본 방법에서는 DUT(Device Under Test: 검사대상이 되는 소자)와 BIST 회로가 동일한 칩 상에 설계되어 있기 때문에 측정할 때 단지 디지털 전자계와 고주파 전압 발생기만이 필요하며, 측정이 간단하고 비용이 저렴하다는 장점이 있다. BIST 회로가 차지하는 면적은 RF front end가 차지하는 전체면적의 약 10%에 불과하다. 본 논문에서 제안하는 검사기술을 이용하여 시뮬레이션해 본 결과 catastrophic 결함에 대해서는 100%, parametric 변동에 대해서는 약 79%의 결함을 검출할 수 있었다.

• Proceedings of the Korea Concrete Institute Conference
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• 2005.05a
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• pp.9-14
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• 2005

The Burj Dubai Project will be the tallest structure ever built by man; when completed the tower will be more than 700 meter tall and more than 160 floors. The early integration of aerodynamic shaping and wind engineering considerations played a major role in the architectural massing and design of this residential tower, where mitigating and taming the dynamic wind effects was one of the most important design criteria. This paper presents a brief overview of the structural system development and considerations of the tower and discusses the construction planning of the key structural components of the tower.