• Title/Summary/Keyword: Built-in Self Test

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A longitudinal analysis on trend of mathematical affective domain (수학 교과에 대한 정의적 특성의 종단적 추이 분석)

  • Kim, Hyunju;Kim, Won Kyung
    • The Mathematical Education
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    • v.55 no.4
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    • pp.447-465
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    • 2016
  • The purpose of this study is to analyze longitudinal trends of students' mathematical affective domain by use of the data mining method. For this purpose, we used the Korea education longitudinal study(KELS 2005) which was the survey data for students' achievement test, affective domain test, teachers' evaluation, and parents' evaluation from $7^{th}$ grader in the year of 2005 to $11^{th}$ grader in the year of 2010. Subjects of this study is a total of 5040 students who answered to the mathematical affective domain survey in KELS 2005. The result findings are as follows. First, students' affective domain had changed negatively as they went up to higher grade. Second, if students' affective domain had built at a certain level in $7^{th}$ grade, the level did not change easily until $11^{th}$ grade. Third, major factors of students' affective domain were shown to be self-efficacy, intrinsic motivation, efforts and patient, and time management.

An BIST for Mixed Signal Circuits (혼성회로를 위한 BIST설계)

  • Bahng, Geum-Hwan;Kang, Sung-Ho;Lee, Young-Hee
    • Proceedings of the Korea Information Processing Society Conference
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    • 2001.10b
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    • pp.1459-1462
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    • 2001
  • 혼성 신호 회로의 설계에 있어 저비용의 고효율 테스트 효율을 보장하기 위해 테스트의 노력은 계속되어 왔다. 특히 테스트를 고려한 BIST(built-in-self-test)설계 방법으로 발전해가고 있는 추세인데, 회로상에서 전체적인 테스트 용이도와 분석에 있어 보다 향상된 방법으로 접근할 수 있고 이러한 시스템에 대해 분석하는데 수월하게 할 수도 있다. 이 논문에서는 효과적인 테스트를 위한 방법을 위해 전압 검출기를 이용한 기준 전압 DC 테스트로써 테스트시간을 감소시키고 효과적인 고장 검출률을 갖는 BIST를 구현하는 것을 제안하였다. 즉 정상적인 회로와 고장회로에서의 동작에서 전압의 파이를 검출하는 회로를 하드웨어상으로 구성함으로써 비용과 시간등을 효과적으로 줄이는 방법을 제안하였다. 실험 결과에서는 기존의 BIST와 비교하여 향상된 것을 나타낸다.

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A Study on the Performance Analysis of an Extended Scan Path Architecture (확장된 스캔 경로 구조의 성능 평가에 관한 연구)

  • 손우정
    • Journal of the Korea Society of Computer and Information
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    • v.3 no.2
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    • pp.105-112
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    • 1998
  • In this paper, we propose a ESP(Extended Scan Path) architecture for multi-board testing. The conventional architectures for board testing are single scan path and multi-scan path. In the single scan path architecture, the scan path for test data is just one chain. If the scan path is faulty due to short or open, the test data is not valid. In the multi-scan path architecture, there are additional signals in multi-board testing. So conventional architectures are not adopted to multi-board testing. In the case of the ESP architecture, even though scan path is either short or open, it doesn't affect remaining other scan paths. As a result of executing parallel BIST and IEEE 1149.1 boundary scan test by using the proposed ESP architecture, we observed that the test time is short compared with the single scan path architecture. By comparing the ESP architecture with single scan path responding to independency of scan path, test time and with multi-scan path responding to signal, synchronization, we showed that the architecture has improved results.

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The Scan-Based BIST Architecture for Considering 2-Pattern Test (2-패턴 테스트를 고려한 스캔 기반 BIST 구조)

  • 손윤식;정정화
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.40 no.10
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    • pp.45-51
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    • 2003
  • In this paper, a scan-based low power BIST (Built-In Self-Test) architecture is proposed. The proposed architecture is based on STUMPS, which uses a LFSR (Linear Feedback Shift Register) as the test generator, a MISR(Multiple Input Shift Register) as the reponse compactor, and SRL(Shift Register Latch) channels as multiple scan paths. In the proposed BIST a degenerate MISR structure is used for every SRL channel; this offers reduced area overheads and has less impact on performance than the STUMPS techniques. The proposed BIST is designed to support both test-per-clock and test-per-scan techniques, and in test-per-scan the total power consumption of the circuit can be reduced dramatically by suppressing the effects of scan data on the circuits. Results of the experiments on ISCAS 89 benchmark circuits show that this architecture is also suitable for detecting path delay faults, when the hamming distance of the data in the SRL channel is considered.

An Effective Cache Test Algorithm and BIST Architecture (효율적인 캐쉬 테스트 알고리듬 및 BIST 구조)

  • Kim, Hong-Sik;Yoon, Do-Hyun;Kang, Sing-Ho
    • Journal of the Korean Institute of Telematics and Electronics C
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    • v.36C no.12
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    • pp.47-58
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    • 1999
  • As the performance of processors improves, cache memories are used to overcome the difference of speed between processors and main memories. Generally cache memories are embedded and small sizes, fault coverage is a more important factor than test time in testing point of view. A new test algorithm and a new BIST architecture are developed to detect various fault models with a relatively small overhead. The new concurrent BIST architecture uses the comparator of cache management blocks as response analyzers for tag memories. A modified scan-chain is used for pre-testing of comparators which can reduce test clock cycles. In addition several boundary scan instructions are provided to control the internal test circuitries. The results show that the new algorithm can detect SAFs, AFs, TFs linked with CFs, CFins, CFids, SCFs, CFdyns and DRFs models with O(12N), where N is the memory size and the new BIST architecture has lower overhead than traditional architecture by about 11%.

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An Efficient Test Pattern Generator for Low Power BIST (내장된 자체 테스트를 위한 저전력 테스트 패턴 생성기 구조)

  • Kim, Ki-Cheol;Kang, Sung-Ho
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.47 no.8
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    • pp.29-35
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    • 2010
  • In this paper we propose a new pattern generator for a BIST architecture that can reduce the power consumption during test application. The principle of the proposed method is to reconstruct an LFSR circuit to reduce WSAs of the heavy nodes by suppressing the heavy inputs. We propose algorithms for finding heavy nodes and heavy inputs. Using the Modified LFSR which consists of some AND/OR gates trees and an original LFSR, BIST applies modified test patterns to the circuit under test. The proposed BIST architecture with small hardware overhead effectively reduces the average power consumption during test application while achieving high fault coverage. Experimental results on the ISCAS benchmark circuits show that average power reduction can be achieved up to 30.5%.

A Structural Model for Health Promotion and Life Satisfaction of Life in College Students in Korea (대학생들의 건강증진행위와 삶의 만족도에 대한 구조모형)

  • Hong, Youn-Lan;Yi, Ga-Eon;Park, Hyun-Sook
    • Research in Community and Public Health Nursing
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    • v.11 no.2
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    • pp.333-346
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    • 2000
  • The purpose of this study was designed to test and develope the structural model that explains health promoting behaviors among college students in Korea. The hypothetical model was constructed on the Pender's Health promotion Model(l996) and the inclusion of some influential factors for life satisfaction. The conceptual framework was built around eight constructs. Exogenous variables included in the model were self-esteem, perceived health status, self-efficacy, internal locus of control, chance locus of control. powerful other locus of control. Endogenous variables were health promotion behaviors and life satisfaction. The results are as follows; 1. The overall fit of the hypothetical model to the data was moderate <$x^2$=4.18(df=11. p=0.041), GFI= 0.99, AGFI= 0.76, RMR= 0.019, CFI= 0.99, CN= 248.50> 2. Path and variable of the model were modified by considering both its theoretical implication and statistical significance of parameter estimates. Compared to the hypothetical model. the revised model has become parsimonious and had a better fit to the data expected in a chi-square value <$x^2$=8.43( df= 16, p=0.21), GFI= 0.99, AGFI= 0.92., RMR= 0.024, CFI= 0.99, CN= 312.01> 3. Some of the predictive factors. especially self efficacy. self esteem. powerful others locus of control. perceived health status revealed the direct effects on health promoting behaviors. Of these variables. self-efficacy was the most signigicant factor. These predictive variables of health promoting behaviors explained 59% of total variances in the model. 4. Health promoting behaviors, self-esteem. and perceived health status revealed direct effect on the life satisfaction. Self-efficacy was identified as an important variable that contributed indirectly to improve life satisfaction by enhancing health promoting behaviors. These predictive variables of life satisfaction explained 42% of total variances in the model. In conclusion. the derived model in this study is considered appropriate in explaining and predicting health promoting models and life satisfaction among college students in Korea and could effectively be used as a reference model for further studies by suggesting a direction in health promoting nursing practices.

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A Study on the Characteristics of Leisure Facilities and Needs of Residents in Apartment Complex (공동주택단지 내 여가시설 특성 및 거주자 요구에 관한 연구)

  • Shin Hwa Kyoung
    • Journal of Families and Better Life
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    • v.22 no.6 s.72
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    • pp.89-97
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    • 2004
  • The purpose of this study was to investigate the characteristics of leisure facilities and to examine residents' needs for leisure facilities in apartment complex. The questionnaire survey and content analysis were used. The Data for content analysis were 476 site plans, and the subjects of questionnaire survey were 673 residents lilving in 35 apartment complex. Frequency, Percentage, and mean, ANOVA-A, x^{2}-test, and multiple regression were used for data analysis. The major results were as follows. 1) Facilities for children play, and senior, sports facilities, community center, green area, and resting place were included in leisure facilities in apartment complex. These facilities were different according to complex site and built-period. 2)The degree of satisfaction of leisure facilities was lower than neutral. The satisfaction of leisure facilities related with diversity of leisure facilities and program, and poor environment. 3) Subjects needed the facilities recommended in housing act including diverse leisure facilities such as sports center and resident's self government facilities. And they needed divers facilities for sports. 4) In terms of location, they needed leisure facilities which was closer to their house.

Window Creativity of a Fashion Store -Its Effects on Consumer Emotions and Behavioral Intentions

  • Choi, Ara;Jang, Ju Yeun;Choo, Ho Jung
    • Journal of the Korean Society of Clothing and Textiles
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    • v.44 no.1
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    • pp.13-32
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    • 2020
  • This study investigates the multi-dimensional structure of fashion store window creativity and examines its effects on consumer responses. Through an expert evaluation survey, this study proposes that fashion store window creativity involves originality, relevance, and artistry. Two experiments are conducted to test the proposed hypotheses. Consumers' emotional responses to the level of window creativity are collected using psychophysiological and self-report methods. Fashion store window creativity has positive effects on psychophysiological affective responses. When the three dimensions of creativity are specified as explanatory factors of emotional responses, relevance and artistry show positive effects on arousal and pleasure, whereas originality has a negative effect on pleasure. Its effect on attitudes is mediated by arousal and pleasure; in addition, the effect on entering intentions is mediated by arousal. Attitudes toward window display also have a positive effect on entering intentions. This study extends existing research on creativity in marketing into the context of visual merchandising in fashion store windows. Findings provide meaningful implications in that the effects of fashion store window creativity on emotions affect consumer attitudes and behavioral intention. By adopting multiple approaches in the empirical phase of this study, the findings are built on strong reliability and validity.

A Study on the Behavioral technology Synthesis of VHDL for Testability (검사 용이화를 위한 VHDL의 동작기술 합성에 관한 연구)

  • Park, Jong-Tae;Choi, Hyun-Ho;Her, Hyong-Pal
    • Journal of the Institute of Electronics Engineers of Korea TE
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    • v.39 no.4
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    • pp.329-334
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    • 2002
  • For the testability, this paper proposed the algorithm at autonomous synthesis which includes the data path structure as the self testing as possible on high level synthesis method when VHDL, coding is used in the system design area. In the proposed algorithm of this paper, MUXs and registers are assigned to the data path of designed system. And the designed data path could be mapped the H/W specification of described VHDL coding to the testable library. As a results, it was mapped H/W to the assign algorithm that is minimized MUX and the registers in collision graph.