• Journal of Power Electronics
• /
• v.19 no.4
• /
• pp.846-857
• /
• 2019

Voltage step-down converters are very popular in distributed power systems, voltage regular modules, electric vehicles, etc. However, a high step-down voltage ratio is required in many applications to prevent the traditional buck converter from operating at extreme duty cycles. In this paper, a series capacitor interleaved buck converter with a soft switching technique is proposed. The DC voltage ratio of the proposed converter is half that of the traditional buck converter and the voltage stress across the one main switch and the diodes is reduced. Moreover, by paralleling the series connected auxiliary switch and the auxiliary inductor with the main inductor, zero voltage transition (ZVT) of the main switches can be obtained without increasing the voltage or current stress of the main power switches. In addition, zero current turned-on and zero current switching (ZCS) of the auxiliary switches can be achieved. Furthermore, owing to the presence of the auxiliary inductor, the turned-off rate of the output diodes can be limited and the reverse-recovery switching losses of the diodes can be reduced. Thus, the efficiency of the proposed converter can be improved. The DC voltage gain ratio, soft switching conditions and a design guideline for the critical parameters are given in this paper. A loss analysis of the proposed converter is shown to demonstrate its advantages over traditional converter topologies. Finally, experimental results obtained from a 100V/10V prototype are presented to verify the analysis of the proposed converter.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.42 no.4
• /
• pp.864-870
• /
• 2017

This paper describes a Dual Buck Converter with mode control using variable Frequency to Voltage for portable devices requiring wide load current. The inherent problems of PLL compensation and efficiency degradation in light load current that the conventional hysteretic buck converter has faced have been resolved by using the proposed Dual buck converter which include improved PFM Mode not to require compensation. The proposed mode controller can also improve the difficulty of detecting the load change of the mode controller, which is the main circuit of the conventional dual mode buck converter, and the slow mode switching speed. the proposed mode controller has mode switching time of at least 1.5us. The proposed DC-DC buck converter was implemented by using $0.18{\mu}m$ CMOS process and die size was $1.38mm{\times}1.37mm$. The post simulation results with inductor and capacitor including parasitic elements showed that the proposed circuit received the input of 2.7~3.3V and generated output of 1.2V with the output ripple voltage had the PFM mode of 65mV and 16mV at the fixed switching frequency of 2MHz in hysteretic mode under load currents of 1~500mA. The maximum efficiency of the proposed dual-mode buck converter is 95% at 80mA and is more than 85% efficient under load currents of 1~500mA.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.12 no.4
• /
• pp.607-614
• /
• 2017

In this research, buck converter was designed and manufactured to improve the wireless charging of smartphone through PWM control technology based on micro controller. A feedback control circuit was fabricated using a voltage sensor so that the output voltage follows the reference voltage. The buck converter, 311V is output as 12V, DC voltage 12V is connected wirelessly, and 5V charge voltage is output. We also confirmed the availability of the buck converter for wireless charging of smart phone through experiments.

• The Transactions of the Korean Institute of Power Electronics
• /
• v.15 no.5
• /
• pp.394-400
• /
• 2010

In this paper, We proposed electronic ballast that applys Buck Converter operation principle to Full-Bridge inverter. The proposed ballast consists of an EMI Filter, a full-bridge rectifier, a passive power factor correction (PFC) circuit and a full-bridge inverter. The passive PFC is used and a Full-Bridge inverter operation by two frequency. High Side and Low Side switch was driven by high frequency and low frequency and realized buck Converter's operation. The lamp is driven by Low Frequency square wave to avoid Acoustic Resonance. Also, bulk of inductor is reduced by high frequency switching. Performance of the proposed ballast was validated through computer simulation using Pspice, experimentation and by applying it to an electronic ballast for a prototype 700W MHL.

• 한국태양에너지학회:학술대회논문집
• /
• 2009.11a
• /
• pp.377-382
• /
• 2009

modelling of the buck converter in photovoltaic power conditioning system is not a possibility of doing with input-output relationship from existing procedures. Because the input current and voltage of the buck converter in fluctuate at any time. The controller which design with the method which has like this error cannot have a good efficiency. In this paper, firstly, in order to design accurate controller of buck converter, new model is proposed. The modeling used a state-space averaging method and came to accomplish. Secondly, the process which design the controller is described. Finally, the simulation results are analyzed.

• Journal of IKEEE
• /
• v.23 no.1
• /
• pp.68-73
• /
• 2019

This paper presents a novel fast shut-down scheme for Buck converter by using a coupled inductor. Generally, a controller for Buck converter stops generating PWM patterns in various fault cases: Overcurrent, Short circuit, or Overvoltage, but the inductor and capacitor keep supplying their stored energy to loads although the switching operations in Buck converter stopped. The stored energy in the inductor and capacitor could cause electrical stresses on breakers and safety problems. The main idea of the proposed fast shutdown scheme is to demagnetize the inductor core by using a coupled inductor, and its performance and operations are verified by using PSIM Simulation.

• Journal of Power Electronics
• /
• v.12 no.3
• /
• pp.410-417
• /
• 2012

In this paper, a direct current control method based on a one-cycle controller (DCOCC) for double frequency buck converters (DF buck) is proposed. This control method can make the average current through the high frequency and low frequency inductors of a DF buck converter equal. This is similar to the average current control method. However, the design of the loop compensator is much easier when compared with the average current control. Since the average current though the high frequency and low frequency inductors is equivalent, the current stress of the high frequency switches and the switch losses are minimized. Therefore, the efficiency of the DF buck converter is improved. Firstly, the operation principle of DCOCC is described, then the small signal models of a one cycle controller and a DF buck converter are presented based on the state space average method. Eventually, a system block diagram of the DCOCC controlled DF buck is established and the compensator is designed. Finally, simulation and experiment results are given to verify the correction of the theory analysis.

• IEIE Transactions on Smart Processing and Computing
• /
• v.4 no.5
• /
• pp.371-378
• /
• 2015

In this paper, a different type of pulse width modulation (PWM) control scheme for a buck converter is introduced. The proposed buck converter uses PWM with frequency hopping and a low quiescent.current low dropout (LDO) voltage regulator with a power supply rejection ratio enhancer to reduce high spurs, harmonics and output voltage ripples. The low quiescent.current LDO voltage regulator is not described in this paper. A three-bit binary-to-thermometer decoder scheme and voltage ripple controller (VRC) is implemented to achieve low voltage ripple less than 3mV to increase the efficiency of the buck converter. An internal clock that is synchronized to the internal switching frequency is used to set the hopping rate. A center frequency of 2.5MHz was chosen because of the bluetooth low energy (BLE) application. This proposed DC-DC buck converter is available for low-current noise-sensitive loads such as BLE and radio frequency loads in portable communications devices. Thus, a high-efficiency and low-voltage ripple is required. This results in a less than 2% drop in the regulator's efficiency, and a less than 3mV voltage ripple, with -26 dBm peak spur reduction operating in the buck converter.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.48 no.6
• /
• pp.25-32
• /
• 2011

This paper proposes high efficiency current-mode DC-DC buck converter that are suitable for portable devices. The current-mode DC-DC buck converter using adjustable Dead-time control method improves the power efficiency 2~5%. The buck converter has been implemented with a standard 0.35${\mu}m$ CMOS process. The size of this chip is 0.97$mm^2$. The input range of the fabricated DC-DC buck converter is 2.5V~3.3V, and the output is 1.8V. The maximum loading current of the converter is 500mA and the peak efficiency is 93% at 200mA loads.

• Proceedings of the KIPE Conference
• /
• 2003.07b
• /
• pp.773-776
• /
• 2003

This paper presents modeling and analysis of a PWM buck AC-AC converter The converter is modelled by using DQ transformation whereby both the static and dynamic characteristics are analyzed completely. The feedforward-feedback control technique is also proposed to obtain instantaneous duty level change whereby very fast dynamic response is achieved. The simulation results show the validity of the modeling and analysis.