• Journal of Power Electronics
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• 제17권5호
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• pp.1173-1185
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• 2017

In this paper, a new single phase multilevel inverter topology with a single DC source is presented. The proposed topology is developed based on the concepts of the L-Z source inverter and the switched capacitor multilevel inverter. The input voltage to the proposed inverter is boosted by two steps: the first step by an impedance network and the second step by switched capacitor units. Compared to other existing topologies, the presented topology can produce a higher boosted multilevel output voltage while using a smaller number of components. In addition, it provides more flexibility to control boosting factor, size, cost and complexity of the inverter. The proposed inverter possesses all the advantages of the L-Z source inverter and the switched capacitor multilevel inverter like controlling the start-up inrush current and capacitor voltage balancing using a simple switching strategy. The operating principle and general expression for the different parameters of the proposed topology are presented in detail. A phase disposition pulse width modulation strategy has been developed to switch the inverter. The effectiveness of the topology is verified by extensive simulation and experimental studies on a 7-level inverter structure.

• Journal of Power Electronics
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• 제18권2호
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• pp.432-444
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• 2018

This paper presents a capacitor voltage balancing topology using a three-level boost converter (TLBC) for a neutral point clamped (NPC) three-level inverter fed surface permanent magnet synchronous motor drive (SPMSM). It enhanced the performance of the drive in terms of its voltage THD and torque pulsation. The main attracting feature of the proposed control is the boosting of the input voltage and at the same time the balancing of the capacitor voltages. This control also reduces the computational complexity. For the purpose of close loop vector control, a software based cost effective resolver to digital converter RDC-less estimation is implemented to calculate the speed and position. The proposed drive is simulated in the MATLAB/SIMULINK environment and an experimental investigation using dSPACE DS1104 validates the proposed drive system at different operating condition.

• Journal of Power Electronics
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• 제18권4호
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• pp.1067-1074
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• 2018

This paper presents a control method for variable-speed motor drives that do not use a DC-link electrolytic capacitor. The proposed circuit consists of a power factor correction converter for boosting the DC-link voltage, an inverter for driving the motor, and a small DC-link film capacitor. By employing a small DC-link capacitor, the proposed circuit that is small, and a low cost and weight are achieved. However, because the DC-link voltage varies periodically, the control of the circuit is more difficult than that of the conventional method. Using the proposed control method, an inverter can be controlled reliably even when the capacitance of the DC-link capacitor is very small. Experiments are performed using a 1.5-kW inverter with a $20-{\mu}F$ DC-link capacitor, and the experimental results are analyzed thoroughly.

• Journal of Power Electronics
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• 제18권4호
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• pp.1051-1066
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• 2018

This study presents a novel step-up switched capacitor multilevel inverter (SCMLI) structure. The proposed structure comprises 2 unequal DC voltage sources, 4 capacitors, and 14 unidirectional power switches. It can synthesize 21 output voltage levels. The important features of the proposed topology are its self-voltage boosting and inherent capacitor voltage balancing capabilities. Furthermore, a cascaded structure of the proposed SCMLI with an asymmetric DC voltage source configuration is presented. The proposed topology and its cascaded structure are compared with conventional and other recently developed topologies in terms of different aspects, such as the required components to produce a specific number of output voltage levels, the total standing voltage (TSV) and peak inverse voltage of the structure, and the maximum number of switches in the conducting path. Furthermore, a cost function is developed to verify the cost-effectiveness of the proposed topology with respect to other topologies. The TSV of the proposed topology is significantly lower than those of other topologies. Moreover, the developed topology is cost-effective compared with other topologies. A detailed operating principle, power loss analysis, and selection procedure for switched capacitors are presented for the proposed SCMLI structure. Extensive simulation and experimental studies of a 21-level inverter structure prove the effectiveness and merits of the proposed SCMLI.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2008년도 하계학술대회 논문집
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• pp.265-267
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• 2008

As generally recognized, the driving performance of a SRM at higher speed will be degraded due to the effects of back electromagnetic force (EMF). This phenomenon can be improved via voltage boosting. So in this paper an improved converter of enhancing the performance for four-phase switched reluctance motor (SRM) is proposed. By using one additional capacitor and switches, an extra controllable boosted voltage can be produced during the rise and fall periods of a motor phase current. Then this active boosted voltage can reduce the effect of EMF on the current, particularly at high speeds. The attractive features of the proposed converter are as follows: obtaining boosted voltage to improve performance of SRM with same numbers of switch and diode as asymmetric converter, having higher control flexibility and capability of boosting voltage compared with passive boosting converters, possessing lower cost and simple control in comparison with existing active boosting converters. The performances of the proposed circuit are verified by the simulation and experiment results.

• 전기학회논문지P
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• 제63권4호
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• pp.361-367
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• 2014

This paper is related to a new solar power conditioner for a built-in step-up chopper function. In the first step-up chopper proposed solar PV power conditioner for mutually connected in series with the input voltage of the bypass diodes are respectively connected to the positive terminal should install the mutual boosting chopper diode connected in series with the boost chopper switching element between the two power supply and at the same time the first and the second was connected to a second diode and a resonance inductor and a snubber capacitor in series with each other. And the common connection point between the bypass diode and the step-up chopper and the step-up chopper diode common connection point of the switching elements of the input voltage was set to the boost inductor for storing energy. In addition, between the step-up chopper and the step-up chopper diode and a switching element of a joint connection point of the first auxiliary diode and the second common connection point of the auxiliary diode was provided, the resonance capacitor. Between the step-up chopper and the step-up chopper diode and a switching element of a joint connection point and the common connection point of the resonance inductor snubber capacitor and connecting the third secondary diode, between two power supply lines is characterized by configuring the DC link capacitor bus lines in parallel. Therefore, it is possible to suppress the switching loss through, DC link bus lines, as well as there could seek miniaturization and weight reduction of the power conditioner itself by using a common capacitor of the non-polar non-polar electrolytic capacitor having a capacitor, the service life of the circuit can be extended and it is possible to greatly reduce the loss can be greatly improve the reliability of the product and the operation of the product itself.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2013년도 추계학술대회 논문집
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• pp.105-106
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• 2013

This paper proposes a new topology with active switched-capacitor and switched-inductor impedance network, which can obtain a high boost factor with small shoot-through time. The proposed topology uses an active switched capacitor and switched-inductor impedance network in order to couple the main circuit and input dc source for boosting the output voltage. The proposed topology contains all advantages of the classical Z-source inverter. Comparing with other topologies, the proposed topology uses lesser component and the voltage boost inversion ability significantly increases. The theoretical analysis, pulse width modulation control strategies, and a comparison with classical ZSI have been given in this paper. Both simulation and experimental results will be presented to verify the advantages of the proposed topology.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 하계종합학술대회논문집
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• pp.863-866
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• 1998

In this paper two quick boosting charge pump circuits for high-speed EEPROM memory are proposed. In order to improve initial charge transfer efficiency, one uses weighted capacitors where each stage has different clock coupling capacitance, and the other uses a multi-path structure at the first stage. SPICE simulation results show that these charge pumps have improve drising-time characteristics, but their $V_{DD}$ mean currents are increased a little compared with conventioanl charge pumps. The rising time upt o 15V of the proposed charge pumps is 3 times faster than that of dickson's pump at the cost of 1.5 tiems more $V_{DD}$ mean current.rrent.

• 한국전자파학회논문지
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• 제23권3호
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• pp.361-366
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• 2012

본 논문에서는 TSMC 0.18 ${\mu}m$ CMOS 공정을 사용하여 저전력, 5.2 GHz 대역 저잡음 증폭기를 설계하였다. 제안된 회로는 5.2 GHz 대역 저잡음 증폭기 설계를 위해, 공통 게이트 구조를 이용하여 입력 정합을 하였다. 입력 정합단에 캐패시터 크로스 커플링 방법을 사용하여 적은 양의 전류를 흘려 적당한 이득을 얻었다. 추가적인 전력 소비 없이 부족한 이득을 증가시키기 위하여 전류 재사용 방법을 이용하여 공통 게이트 증폭단 위에 공통 소스 구조를 추가하였다. 전류 재사용단의 인덕터의 크기를 줄이기 위하여 캐패시터를 병렬로 연결함으로써 실효 인덕턴스 값을 증가시켜 인덕터의 크기를 줄였다. 제안된 회로는 5.2 GHz 대역에서 17.4 dB의 이득과 2.7 dB의 잡음 지수 특성을 갖는다. 저잡음 증폭기는 1.8 V의 공급 전압에 대해 5.2 mW의 전력을 소비한다.

• Journal of Electrical Engineering and Technology
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• 제9권2호
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• pp.589-599
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• 2014

On the basis of the traditional ZSI (Z-source inverter), this paper presents a ESL-${\Gamma}$-ZSI, which uses a unique ${\Gamma}$-shaped impedance network and an extended SL network for boosting its output voltage in addition to their usual voltage-buck behavior. The inverter can increase the boost factor through adjusting shoot-through duty ratio and increasing the number of inductors. Capacitor voltage stress of ESL-${\Gamma}$-ZSI is a constant when 1>D>0, and ESL-${\Gamma}$-ZSI has small inductor current stress. The working principle of ESL-${\Gamma}$-ZSI and comparison with the classical ZSI and SL- ZSI are analyzed in detail. The power loss comparison between ESL-${\Gamma}$-ZSI and Cuk converter is analyzed detailedly. Simulation and experimental results are given to demonstrate the operation features of the inverter.