• Korean Chemical Engineering Research
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• 제54권2호
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• pp.274-277
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• 2016

Effects of interlayer insertion between multi-quantum well and electron blocking layer of green light emitting diode on diode performances were studied by device simulation. Dependence of Mg doping depth on characteristics of current-voltage, emitting wavelength, leakage current, and external quantum efficiency was investigated, and the optimum diode structure was presented. Device structures with interlayers doped in entire region and up to 30 nm showed remarkable reduced leakage current and effectively relieved efficiency droop which is one of the biggest challenges in green light emitting diode. Furthermore, the most improved characteristics in current-voltage and electroluminescence was obtained by the latter structure.

• Journal of Satellite, Information and Communications
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• 제9권2호
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• pp.12-17
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• 2014

In this paper, modified EDNMOS device with DPS (double polarity source) structure are suggested to realize stable and robust ESD (electrostatic discharge) protection performance of high voltage operating microchip. This DPS structure inserts the P+ diffusion layer on N+ source side, which in intended to block lateral extension of the electron rich region from N+ source side. Based on our simulation results, the inserted P+ diffusion layer effectively prevents the formation of deep electron channeling induced by high electron injection. As a result, our proposed DPS_EDNMOS devices could overcome the double snapback effect of conventional Std_EDNMOS device.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 한국전기전자재료학회 2000년도 하계학술대회 논문집
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• pp.751-754
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• 2000

When charge-trap SONOS cells are used flash memory, the tunneling program/erase condition to minimize the generation of interface traps was investigated. SONOSFET NVSM cells were fabricated using 0.35$\mu\textrm{m}$ standard memory cell embedded logic process including the ONO cell process. based on retrograde twin-well, single-poly, single metal CMOS process. The thickness of ONO triple-dielectric for memory cell is tunnel oxide of 24${\AA}$, nitride of 74 ${\AA}$, blocking oxide of 25 ${\AA}$, respectively. The program mode(Vg: 7,8,9 V, Vs/Vd: -3 V, Vb: floating) and the erase mode(Vg: -4,-5,-6 V, Vs/Vd: floating, Vb: 3V) by modified Fowler-Nordheim(MFN) tunneling were used. The proposed programming condition for the flash memory of SONOSFET NVSM cells showed less degradation($\Delta$Vth, S, Gm) characteristics than channel MFN tunneling operation. Also the program inhibit conditions of unselected cell for separated source lines NOR-tyupe flash memory application were investigated. we demonstrated that the program disturb phenomenon did not occur at source/drain voltage of 1 V∼4 V and gate voltage of 0 V∼4.

• Journal of the Korean Society of Industry Convergence
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• 제21권6호
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• pp.361-368
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• 2018

This paper proposes a grid - connected CTTS system that can be soft switched to meet the government's effective resource allocation policy for emergency generator. In order to eliminate the system instability caused by the large inrush current generation in the system switching, a new virtual rotation coordinate method for the dissimilar power source is proposed. The proposed virtual rotation coordinate method improves the voltage detection accuracy of the voltage difference of the dissimilar power supply, and it is proved that the synchronous switching characteristic is excellent. In addition, zero current and system stabilization can be achieved by realizing zero current when blocking CTTS with instantaneous reactive power control. Simulation was carried out to verify the validity of the proposed method, and the 500[kVA] system was fabricated and verified to demonstrate the superiority of the proposed method.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 한국전기전자재료학회 2009년도 하계학술대회 논문집
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• pp.305-306
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• 2009

In this study, we have invastigated the recombination zone in the blue phosphorescent organic light-emitting devices with various partially doped structures. The basic device structure of the blue PHOLED was anode / hole injection layer (HIL) / hole transport layer (HTL) / emittingvastigated the recombination zone in the blue layer (EML) / hole blocking layer (HBL) / electron transport layer (ETL) / electron injection layer (EIL) / cathode. After the preparation of the blue PHOLED, the current density (J) - voltage (V) - luminance (L) and current efficiency characteristics were measured.

• Journal of Electrical Engineering and Technology
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• 제6권2호
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• pp.167-173
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• 2011

This paper presents a method for the development of the impedance locus to test the dynamic characteristics of protective relays. Specifically, using the proposed method, the impedance locus can comprise three impedance points, and the speed of impedance trajectory can be adjusted by frequency deviation. This paper is divided into two main sections. The first section deals with the configuration of impedance locus with voltage magnitude, total impedance magnitude, and impedance angle. The second section discusses the control of the locus speed with the means of the deviation between two frequencies. The proposed method is applied to two machine equivalent systems with offline simulation (i.e., PSCAD) and real-time simulation (i.e., real-time simulation environment) to demonstrate its effectiveness.

• The Transactions of the Korean Institute of Electrical Engineers A
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• 제51권9호
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• pp.451-459
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• 2002

This paper presents a method for modelling of the impedance locus in order to test the protective relay with dynamic. This paper has the two parts, the first part is the configuration of impedance locus with voltage magnitude, total impedance magnitude and angle. And the second part is the control of the locus speed with deviation of two frequencies. The proposed method is applied to two machine equivalent system with PSCAD/EMTDC to show its effectiveness.

• Proceedings of the KIPE Conference
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• 전력전자학회 1999년도 전력전자학술대회 논문집
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• pp.295-298
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• 1999

In this paper, the diode bridge-type ZVT(Zero-Voltage Transition) inverter is proposed. It consists of one auxiliary switch, three resonant inductors and six blocking diodes. So, the advantage of the proposed topology is the reduction of the auxiliary switch. The topology of the proposed ZVT inverter is analyzed with a description of the control conditions based on the load current. Therefore, this paper two control algorithms were discussed. A variable resonant pattern control algorithm by using load current feedback and a resonant period control algorithm by using resonant inductor current feedback is proposed in order to achieve the ZVT switching condition in full control range and the reducing current spike main switches cause by reverse recovery problem.

• Journal of Power Electronics
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• 제10권1호
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• pp.14-20
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• 2010

In this paper, a tightly regulated triple output asymmetrical half bridge flyback (ASHF) converter is proposed. In order to regulate all output voltages, pulse frequency modulation (PFM), pulse width modulation (PWM) and phase delay (PD) are used simultaneously. In comparison with the conventional PWM-PD method, the interactions among the control variables are minimized and the operating range is increased. By the utilization of a multi winding transformer, the auxiliary transformer and the blocking capacitor are eliminated and the size and cost of the proposed converter is reduced. The operation principle of the converter is explained and the modes of operation are investigated. Based on the results, the steady state characteristics of the converter are explored. A 24V/10A, 12V/5A, 5V/10A hardware prototype is built and tested to verify the analysis results and the voltage regulation of the triple outputs of the proposed converter.

• The Transactions of the Korean Institute of Electrical Engineers B
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• 제49권9호
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• pp.598-606
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• 2000

This paper proposes a new snubber circuit for 4-level inverter and converter. The snubber circuit makes use of Undeland snubber and McMurray efficient snubber as basic snubber unit and can be regarded as a generalized combined Undeland and McMurray efficient snubber. The proposed snubber keeps such good features as fewer number of components improved efficiency due to low snubber loss capability of clamping overvoltage across main switching devices and no unbalance problem of blocking voltage. Furthermore the proposed concept of constructing a snubber circuit for 4-level inverter and converter can apply to any level of converterand inverter.