• Journal of the Institute of Electronics and Information Engineers
• /
• v.53 no.10
• /
• pp.103-108
• /
• 2016

With the growing trend of pervasive computing, (the idea that technology is moving beyond personal computers to everyday devices) there is a growing demand for lightweight ciphers to safeguard data in a network that is always available. For all block cipher applications, the AES is the preferred choice. However, devices used in pervasive computing have extremely constraint environment and as such the AES will not be suitable. In this paper we design and implement a new lightweight compact block cipher that takes advantage of both S-P network and the Feistel structure. The cipher uses the S-box of PRESENT algorithm and a key dependent one stage omega permutation network is used as the cipher's P-box. The cipher is implemented on iNEXT-V6 board equipped with virtex-6 FPGA. The design synthesized to 196 slices at 337 MHz maximum clock frequency.

• Journal of the Korea Institute of Information Security & Cryptology
• /
• v.28 no.5
• /
• pp.1071-1078
• /
• 2018

Recently, a family of lightweight block ciphers CHAM that has effective performance on resource-constrained devices is proposed. The CHAM uses a stateless-on-the-fly key schedule method which can reduce the key storage areas. Furthermore, the core design of CHAM is based on ARX(Addition, Rotation and XOR) operations which can enhance the computational performance. Nevertheless, we point out that the CHAM algorithm may be vulnerable to the fault injection attack which can reveal 4 round keys and derive the secret key from them. As a simulation result, the proposed fault injection attack can extract the secret key of CHAM-128/128 block cipher using about 24 correct-faulty cipher text pairs.

• Journal of the Korea Institute of Information Security & Cryptology
• /
• v.29 no.4
• /
• pp.709-718
• /
• 2019

A lightweight block cipher CHAM designed for suitability in resource-constrained environment has reasonable security level and high computational performance. Since this cipher may contain intrinsic weakness on side channel attack, it should adopt a countermeasure such as masking method. In this paper, we implement the masked CHAM cipher on 32-bit microprosessor Cortex-M3 platform to resist against side channel attack and analyze their computational performance. Based on the shortcoming of having many round functions, we apply reduced masking method to the implementation of CHAM cipher. As a result, we show that the CHAM-128/128 algorithm applied reduced masking technique requires additional operations about four times.

• The Journal of Society for e-Business Studies
• /
• v.6 no.1
• /
• pp.17-33
• /
• 2001

EC(Electronic Commerce) which is done on the virtual space through Internet has strong point like independence from time and space. On the contrary, it also has weak point like security problem because anybody can access easily to the system due to open network attribute of Internet, Therefore, we need the solutions that protect the EC security problem for safe and useful EC activity. One of these solutions is the implementation of strong cipher system. YK2(Young Ku King) cipher system proposed in this paper is good solution for the EC security and it overcome the limit of current block cipher system using 128 bits key length for input, output, encryption key and 32 rounds. Moreover, it is designed for the increase of time complexity by adapting more complex design for key scheduling algorithm regarded as one of important element effected to encryption.

• Journal of IKEEE
• /
• v.24 no.2
• /
• pp.468-474
• /
• 2020

This paper describes the hardware implementation of SPECK, a lightweight block cipher algorithm developed for the security of applications with limited resources such as IoT and wireless sensor networks. The block cipher SPECK crypto-core supports 8 block/key sizes, and the internal data-path was designed with 16-bit for small gate counts. The final round key to be used for decryption is pre-generated through the key initialization process and stored with the initial key, enabling the encryption/decryption for consecutive blocks. It was also designed to process round operations and key scheduling independently to increase throughput. The hardware operation of the SPECK crypto-core was validated through FPGA verification, and it was implemented with 1,503 slices on the Virtex-5 FPGA device, and the maximum operating frequency was estimated to be 98 MHz. When it was synthesized with a 180 nm process, the maximum operating frequency was estimated to be 163 MHz, and the estimated throughput was in the range of 154 ~ 238 Mbps depending on the block/key sizes.

• Korean Journal of Optics and Photonics
• /
• v.24 no.5
• /
• pp.262-270
• /
• 2013

In this paper, we propose a modified optical CBC(Cipher Block Chaining) encryption method using optical XOR logic operations. The proposed method is optically implemented by using dual encoding and a free-space interconnected optical logic gate technique in order to process XOR operations in parallel. Also, we suggest a CBC encryption/decryption optical module which can be fabricated with simple optical architecture. The proposed method makes it possible to encrypt and decrypt vast two-dimensional data very quickly due to the fast optical parallel processing property, and provides more security strength than the conventional electronic CBC algorithm because of the longer security key with the two-dimensional array. Computer simulations show that the proposed method is very effective in CBC encryption processing and can be applied to even ECB(Electronic Code Book) mode and CFB(Cipher Feedback Block) mode.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2015.05a
• /
• pp.401-403
• /
• 2015

This paper describes an efficient hardware design of 128-bit block cipher algorithm LEA(lightweight encryption algorithm). In order to achieve area-efficient and low-power implementation, round block and key scheduler block are optimized to share hardware resources for encryption and decryption. The key scheduler register is modified to reduce clock cycles required for key scheduling, which results in improved encryption/decryption performance. FPGA synthesis results of the LEA processor show that it has 2,364 slices, and the estimated performance for the master key of 128/192/256-bit at 113 MHz clock frequency is about 181/162/109 Mbps, respectively.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.25 no.3A
• /
• pp.399-405
• /
• 2000

In this paper, we deal with block cipher algorithm IDEA(international data encryption algorithm), previously known as typical block cipher system. first of all, analysing key scheduler we classify the key sequences with the used key bit and the unused key bits in each round. with this properties we propose the two method, which are differential analysis using differences of plaintext pairs and linear analysis using LSB bit of plaintexts and key sequences.

• The KIPS Transactions:PartA
• /
• v.17A no.6
• /
• pp.275-280
• /
• 2010

In this paper, we discuss and propose an efficiently parallelized block cipher algorithm on the CELL BE processor. With considering the heterogeneous feature of the CELL BE architecture, we apply different encoding/decoding methods to PPE and SPE and improve the throughput. Our implementation was fully tested, with execution results showing achievement of high throughput, capable of supporting as high network speed as 2.59 Gbps. Compared to various parallel implementations on multi-core systems, our approach provides speedup of 1.34 in terms of encoding/decoding speed.

• Current Optics and Photonics
• /
• v.5 no.2
• /
• pp.155-163
• /
• 2021

We propose a novel optical encryption scheme for cipher-feedback-block (CFB) mode, capable of encrypting two-dimensional (2D) page data with the use of two-step phase-shifting digital interferometry utilizing orthogonal polarization, in which the CFB algorithm is modified into an optical method to enhance security. The encryption is performed in the Fourier domain to record interferograms on charge-coupled devices (CCD)s with 256 quantized gray levels. A page of plaintext is encrypted into digital interferograms of ciphertexts, which are transmitted over a digital information network and then can be decrypted by digital computation according to the given CFB algorithm. The encryption key used in the decryption procedure and the plaintext are reconstructed by dual phase-shifting interferometry, providing high security in the cryptosystem. Also, each plaintext is sequentially encrypted using different encryption keys. The random-phase mask attached to the plaintext provides resistance against possible attacks. The feasibility and reliability of the proposed CFB method are verified and analyzed with numerical simulations.