• Journal of the Korea Institute of Military Science and Technology
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• v.17 no.3
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• pp.336-341
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• 2014

When using a higher-order modulation scheme, there are variations in bit-reliability depending on the bit position in a modulation symbol. Variations of bit-reliability in the codeword block lower the decoding performance. Also, the decoding performance increases as the sum of the bit-reliabilities in the codeword block increases. This paper presents a novel hybrid automatic repeat request scheme that increases the sum of the reliabilities of the transmitted bits by lowering the modulation order, and decreases the variations of bit-reliability in the codeword block by preferentially retransmitting bits with low reliability. The proposed scheme outperforms the constellation rearrangement scheme. Furthermore, the proposed scheme also provides a good solution in cases where the size of the retransmission block is smaller than the size of the initial transmission block.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.12C
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• pp.1135-1141
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• 2007

In this paper, an adaptive bit-reliability mapping is proposed for the bit-level Chase combining in LDPC-coded high-order modulation systems. Contrary to the previously known bit-reliability mapping that assigns the information (or parity) bits to more (or less) reliable bit positions, the proposed mapping adaptively assigns codeword bits to the bit positions of various reliabilities by considering the characteristics of code and protection levels of bits in high-order modulation symbol. Compared with the symbol-level Chase combining and the constellation rearrangement bit mapping, the proposed mapping gives $0.7{\sim}1.3$ dB and $0.1{\sim}1.0$ dB performance gain at $FER=10^{-3}$ with no additional complexity, respectively. Adaptive bit-reliability mappings are derived for various environments and the validity of them is confirmed through simulation.

• Journal of Institute of Control, Robotics and Systems
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• v.20 no.4
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• pp.443-448
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• 2014

Soft errors in memory devices that caused by radiation are the main threat from a reliability point of view. This threat can be commonly overcome with the combination of SEC (Single-Error Correction) codes and scrubbing technique. The interleaving architecture can give memory devices the ability of tolerating these soft errors, especially against multiple-bit soft errors. And the interleaving distance plays a key role in building the tolerance against multiple-bit soft errors. This paper proposes a reliability model of an interleaved memory device which suffers from multiple-bit soft errors and are protected by a combination of SEC code and scrubbing. The proposed model shows how the interleaving distance works to improve the reliability and can be used to make a decision in determining optimal scrubbing technique to meet the demands in reliability.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.815-818
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• 2003

New sensing and writing schemes for a magneto-resistive random access memory (MRAM) with a twin cell structure are proposed. In order to enhance the cell reliability, a scheme of the low voltage precharge is employed to keep the magneto resistance (MR) ratio constant. Moreover, a common gate amplifier is utilized to provide sufficient voltage signal to the bit line sense amplifiers under the small MR ratio structures. To enhance the writing reliability, a current mode technique with tri-state current drivers is adopted. During write operations, the bit and /bit lines are connected. And 'HIGH' or 'LOW' data is determined in terms of the current direction flowing through the MTJ cell. With the viewpoint of the improved reliability of the cell behavior and sensing margin, HSPICE simulations proved the validity of the proposed schemes.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.4B
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• pp.208-216
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• 2007

Wireless Sensor Networks (WSNs) are characterized by low capacity on each nodes and links. Wireless links have high bit error rate (BER) parameter that changes frequently due to the changes on network topology, interference, etc. To guarantee reliability in an error-prone environment, a retransmission mechanism can be used. In this mechanism, the number of retransmissions is used as a parameter that controls reliability requirement level. In this paper, we propose an Error Adaptive Transport Protocol (EATP) for WSNs that updates the number of retransmissions regularly to guarantee reliability during bit error rate changes as well as to utilize energy effectively. The said algorithm uses local information, thus, it does not create overhead problem.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.19 no.5
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• pp.599-604
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• 2018

For missile systems, sustaining high reliability and ensuring economical maintenance are very important. In the Republic of Korea, for most missiles, periodic inspection is mandatory for missiles in the field. Every fixed number of years, they are returned to the ordnance depot to be tested and repaired if faults are found. Almost all missiles have a built-in test (BIT) capability. With the BIT, faulty missiles can be isolated anytime during operations or storage in the launchers. So the reliability and the maintenance costs of the missiles greatly depend on the length of the inspection cycle and the BIT/inspection quality. In this paper, we suggest a model for predicting the storage reliability of missiles subjected to non-periodic tests and periodic inspections, excluding overlapping failures. Some numerical examples are given. This model will be useful for determining the length of the periodic inspection cycle.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.2
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• pp.302-312
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• 2012

In this paper, small-area and high-reliability design techniques of a 512-bit EEPROM are designed for UHF RFID tag chips. For a small-area technique, there are a WL driver circuit simplifying its decoding logic and a VREF generator using a resistor divider instead of a BGR. The layout size of the designed 512-bit EEPROM IP with MagnaChip's $0.18{\mu}m$ EEPROM is $59.465{\mu}m{\times}366.76{\mu}m$ which is 16.7% smaller than the conventional counterpart. Also, we solve a problem of breaking 5V devices by keeping VDDP voltage constant since a boosted output from a DC-DC converter is made discharge to the common ground VSS instead of VDDP (=3.15V) in getting out of the write mode.

• The Journal of the Acoustical Society of Korea
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• v.41 no.4
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• pp.410-418
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• 2022

Channel reliability estimation for iterative codes such as turbo codes is very important factor in time varying underwater acoustic channel, an incorrect estimation of channel reliability induced performance degradation. Therefore, this paper presents an optimal channel reliability estimation method for turbo coded FSK signal with rate of 1/3. The estimated BER algorithm is a method that can estimate the reliability of received data by comparing received data and decoded data, and we determine optimal channel reliability by using the method. In order to analyze the performance, the experiment was conducted on a lake in Munkyeong city by moving in the range of 300 m to 500 m. At the result of applying presented method to failed decoding packets, we confirm all packets are decoded successfully.

• IEMEK Journal of Embedded Systems and Applications
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• v.18 no.1
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• pp.31-40
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• 2023

Recent advances in flash technologies, such as 3D processing and multileveling schemes, have successfully increased the flash capacity. Unfortunately, these technology advances significantly degrade flash's reliability due to a smaller cell geometry and a finer-grained cell state control. In this paper, we propose an asymmetric BER-aware reliability optimization technique (aBARO), new flash optimization that improves the flash reliability. To this end, we first reveal that bit errors of 3D NAND flash memory are highly skewed among flash cell states. The proposed aBARO exploits the unique per-state error model in flash cell states by selecting the most error-prone flash states and by forming narrow threshold voltage distributions (for the selected states only). Furthermore, aBARO is applied only when the program time (tPROG) gets shorter when a flash cell becomes aging, thereby keeping the program latency of storage systems unchanged. Our experimental results with real 3D MLC and TLC flash devices show that aBARO can effectively improve flash reliability by mitigating a significant number of bit errors. In addition, aBARO can also reduce the read latency by 40%, on average, by suppressing the read retries.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.17 no.4
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• pp.1296-1309
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• 2023

In this paper, based on the soft cancellation (SCAN) bit-flipping (SCAN-BF) algorithm, a generalized SCAN bit-flipping (GSCAN-BF-Ω) decoding algorithm is carried out, where Ω represents the number of bits flipped or corrected at the same time. GSCAN-BF-Ω algorithm corrects the prior information of the code bits and flips the prior information of the unreliable information bits simultaneously to improve the block error rate (BLER) performance. Then, a joint threshold scheme for the GSCAN-BF-2 decoding algorithm is proposed to reduce the average decoding complexity by considering both the bit channel quality and the reliability of the coded bits. Simulation results show that the GSCAN-BF-Ω decoding algorithm reduces the average decoding latency while getting performance gains compared to the common multiple SCAN bit-flipping decoding algorithm. And the GSCAN-BF-2 decoding algorithm with the joint threshold reduces the average decoding latency further by approximately 50% with only a slight performance loss compared to the GSCAN-BF-2 decoding algorithm.