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Adaptive Bit-Reliability Mapping for LDPC-Coded High-Order Modulation Systems  

Joo, Hyeong-Gun (한양대학교 전자컴퓨터통신공학과 부호 및 통신 연구실)
Hong, Song-Nam ((주)삼성전자 정보 통신 총괄 통신 연구소)
Shin, Dong-Joon (한양대학교 전자컴퓨터통신공학과 부호 및 통신 연구실)
Publication Information
The Journal of Korean Institute of Communications and Information Sciences / v.32, no.12C, 2007 , pp. 1135-1141 More about this Journal
Abstract
In this paper, an adaptive bit-reliability mapping is proposed for the bit-level Chase combining in LDPC-coded high-order modulation systems. Contrary to the previously known bit-reliability mapping that assigns the information (or parity) bits to more (or less) reliable bit positions, the proposed mapping adaptively assigns codeword bits to the bit positions of various reliabilities by considering the characteristics of code and protection levels of bits in high-order modulation symbol. Compared with the symbol-level Chase combining and the constellation rearrangement bit mapping, the proposed mapping gives $0.7{\sim}1.3$ dB and $0.1{\sim}1.0$ dB performance gain at $FER=10^{-3}$ with no additional complexity, respectively. Adaptive bit-reliability mappings are derived for various environments and the validity of them is confirmed through simulation.
Keywords
LDPC codes; High-order modulation; Adaptive bit-reliability mapping; Chase combining;
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