• Journal of IKEEE
• /
• v.20 no.2
• /
• pp.167-170
• /
• 2016

Replica bit-line technique is used for making enable signal of sense amplifier which accurately tracks bit-line of SRAM. However, threshold voltage variation in the replica bit-line circuit changes the cell current, which results in variation of the sense amplifier enable time, $T_{SAE}$. The variation of $T_{SAE}$ makes the sensing operation unstable. In this paper, in addition to conventional replica bit-line delay ($RBL_{conv}$), dual replica bit-line delay (DRBD) and multi-stage dual replica bit-line delay (MDRBD) which are used for reducing $T_{SAE}$ variation are briefly introduced, and the maximum possible number of on-cell which can satisfy $6{\sigma}$ sensing yield is determined through simulation at a supply voltage of 0.6V with 14nm FinFET technology. As a result, it is observed that performance of DRBD and MDRBD is improved 24.4% and 48.3% than $RBL_{conv}$ and energy consumption is reduced which 8% and 32.4% than $RBL_{conv}$.

• The Journal of the Korea Contents Association
• /
• v.7 no.2
• /
• pp.92-99
• /
• 2007

This paper presented a low power design of a 32bit block cypher processor reduced from the original 128bit architecture. The primary purpose of this research is to evaluate physical implementation results rather than theoretical aspects. The data path and diffusion function of the processor were reduced to accommodate the smaller hardware size. As a running example demonstrating the design approach, we employed a modified ARIA algorithm having four S-boxes. The proposed 32bit ARIA processor comprises 13,893 gates which is 68.25% smaller than the original 128bit structure. The design was synthesized and verified based on the standard cell library of the MagnaChip's 0.35um CMOS Process. A transistor level power simulation shows that the power consumption of the proposed processor reduced to 61.4mW, which is 9.7% of the original 128bit design. The low power design of the block cypher Processor would be essential for improving security of battery-less wireless sensor networks or RFID.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.30 no.3C
• /
• pp.64-68
• /
• 2005

Reed-Solomon code is one of the most versatile channel codes. The encoder can be implemented with two famous structures: ordinary and bit-serial. The ordinary encoder is generally known to be complex and fast, while the bit-serial encoder is simple and not so fast. However, it may not be true for a longer codeword length at least in VHDL implementation. In this letter, it is shown that, when the encoder is implemented with VHDL, the number of logic gates of the bit-serial encoder might be larger than that of the ordinary encoder if the dual basis conversion table has to be used. It is also shown that the encoding speeds of the two VHDL implemented encoders are exactly same.

• Journal of Broadcast Engineering
• /
• v.18 no.2
• /
• pp.297-310
• /
• 2013

In this paper, we present a model-based video bit rate estimation scheme for reducing the bit rate while maintaining a subjective quality in many video streaming services limited by network bandwidth, such as IPTV services. First, we extract major parameters which serve as an indirect measurement of frame's bits. Using those parameters, the proposed bit rate estimation scheme can extract candidate frames. Finally, the bit rate of each segment is estimated by statistical analysis and a mathematical model based on a given target quality. In experimental results, we show that the proposed scheme can reduce the bit rate on average by 43% in low-complexity video while maintaining the subjective quality. To find the appropriate bit rate based on video contents, the proposed schemes can estimate the bit rate with neither the repeated full encoding nor subjective quality test. On average, the bit rate can be automatically estimated by encoding the candidate frames of 4%.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.41 no.6
• /
• pp.17-24
• /
• 2004

This paper describes a novel bit line structure to minimize coupling noise induced by coupling capacitance between bit lines. In DRAMs coupling capacitance is inherently present bit lines. As in submicron process the bit line space gets narrower. bit line coupling capacitance increases and this increased coupling capacitance sharply raises cross-talk noise. In this paper using different layers of metal for adjacent bit lines has been tested to reduces cross-talk noise and a novel bit line structure capable of reducing capacitance is introduced and verified.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.46 no.5
• /
• pp.9-14
• /
• 2009

In this paper, we proposed a novel OTP unit bit of CMOS gate oxide antifuse using the standard CMOS process without additional process. The proposed OTP unit bit is composed of 3 transistors including an NMOS gate oxide antifuse and a sense amplifier of inverter type. The layout area of the proposed OTP unit bit is $22{\mu}m^2$ similar to a conventional OTP unit bit. The programming time of the proposed OTP unit bit is 3.6msec that is improved than that of the conventional OTP unit bit because it doesn't use high voltage blocking elements such as high voltage blocking switch transistor and resistor. And the OTP array with the proposed OTP unit bit doesn't need sense amplifier and bias generation circuit that are used in a conventional OTP array because sense amplifier of inverter type is included to the proposed OTP unit bit.

• Proceedings of the IEEK Conference
• /
• 1998.10a
• /
• pp.715-718
• /
• 1998

본 논문에서는 시분할 구조와 1.5bit 디지털 에러보상을 사용하여 작은 면적을 갖는 저 전압, 저전력 10bit 1㎒ 사이클릭 A/D 변환기를 제안하였다. 제안된 사이클릭 A/D 변환기는 시분할 구조를 사용함으로서 변환속도의 향상과 저 전력 특성을 가질 수 있었으며 1.5bit 디지털 에러 보상을 사용함으로서 10bit의 고해상도와 저 전력 특성을 구현할 수 있었다. 제안된 사이클릭 A/D 변환기는 0.6㎛ CMOS Nwell 공정 parameter로 simulation 하였으며 layout 결과 칩면적은 1.1㎜×0.8㎜ 이며 이는 비슷한 성능을 갖는 다른 A/D 변환기에 비하여 매우 작은 크기이다. 제안된 사이클릭 A/D 변환기는 3V의 전원전압에 1.6㎽의 전력소모를 갖는다. Matlab simulation 결과 INL, DNL은 각각 0.6LSB, 0.7LSB 이하의 값을 보였다.

• Proceedings of the Korea Information Processing Society Conference
• /
• 2013.11a
• /
• pp.310-313
• /
• 2013

BitTorrent는 파일 공유를 위하여 가장 널리 사용되고 있는 P2P (Peer to Peer)프로토콜로서, Mesh-Pull 구조를 채용하여 라이브 스트리밍에 대한 연구가 꾸준히 이루어지고 있다. BitTorrent에서는 Peer Wire Protocol을 사용하여 피어들간에 파일조각들을 교환하게 되는데, 이를 위하여 주기적으로 버퍼맵 정보를 HAVE 메시지를 사용하여 브로드캐스트 하는데, 피어의 수가 증가할수록 이로 인한 시그널링 오버헤드가 크게 증가하는 문제를 갖고 있다. 본 논문에서는 이러한 문제를 극복하고 라이브 스트리밍의 성능을 개선하기 위하여 HAVE 메시지를 선택적으로 전송하는 방법을 제안한다. 실험을 통하여, 제안 방식은 기존의 BitTorrent 기반 Mesh-Pull 구조를 채용하는 라이브 스트리밍 방식과 비교하여 HAVE 메시지의 브로드캐스트로 인한 시그널링 오버헤드를 비약적으로 줄일 수 있음을 보였다.

• Proceedings of the Korean Information Science Society Conference
• /
• 2003.04d
• /
• pp.581-583
• /
• 2003

현재 인터넷에서는 사용자의 급격만 증가로 인해 고성능의 라우터를 요구하고 있고 주소부족으로 IPv4에서 IPv6로 변화를 하고 있다. IPv4처럼 IPv6에서도 Address Lookup이 병목이 될 것이며 IPv4와는 달리 IPv6는 128bit의 주소 길이를 가지고 있어 이에 맞는 라우터 구조와 Address Lookup 알고리즘이 필요하다. 본 논문에서는 IPv6주소 128bit 중 외부에서 할당받는 64bit를 3단계로 나누는 계층적 네트워크 구성과 각 단계에 적합한 라우팅 테이블 구조와 Address Lookup 알고리즘에 대해 연구하였고 펜티엄 III 866MHz의 프로세서에서 알고리즘의 검색 시간을 측정해 각 단계에 맞는 라우팅 테이블 구조를 제안하였다.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.46 no.3
• /
• pp.20-25
• /
• 2009

We propose hardware architecture of floating-point square root and inverse square root arithmetic units using lookup tables. They are used for lighting engines and shader processor for 3D graphic processing. The architecture is based on Taylor series expansion and consists of lookup tables and correction units so that the size of look-up tables are reduced. It can be applied to 32 bit floating point formats of IEEE-754 and reduced 24 bit floating point formats. The square root and inverse square root arithmetic units for 32 bit and 24 bit floating format number are designed as the proposed architecture. They can operation in a single cycle, and satisfy the precision of $10^{-5}$ required by OpenGL 1.x ES. They are designed using Verilog-HDL and the RTL codes are verified using an FPGA.