• Transactions on Electrical and Electronic Materials
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• v.17 no.6
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• pp.380-382
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• 2016

The mechanism for instability under PBS (positive bias stress) in amorphous SIZO (Si-In-Zn-O) thin-film transistors was investigated by analyzing the charge trapping mechanism. It was found that the bulk traps in the SIZO channel layer and the channel/dielectric interfacial traps are not created during the PBS duration. This result suggests that charge trapping in gate dielectric, and/or in oxide semiconductor bulk, and/or at the channel/dielectric interface is a more dominant mechanism than the creation of defects in the SIZO-TFTs.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.557-558
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• 2006

In this paper, the hysteresis characteristics by bias stress in organic thin film transistors using inkjet printing were investigated. Electron trapping increased threshold voltage for positive gate bias stress and hole trapping decreased threshold voltage for negative gate bias stress. From these phenomena, highly reproducible measurement method which minimized threshold voltage shift by choosing the proper range of gate voltage was suggested. Using this measurement method, we found that electron trapping as well as hole trapping had important influence on hysteresis characteristics.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.1568-1570
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• 2009

Nanocrystalline silicon thin films were deposited using an internal-type inductively coupled plasma-chemical vapor deposition at room temperature by varying the bias power to the substrate and the structural characteristics of the deposited thin film were investigated. The result showed that the crystalline volume fraction was decreased with the increase of bias power. At the low bias power range of 0~60 W, the compress stress in the deposited thin film was in the range of -34 ~ -77 Mpa which is generally lower than the residual stress observed for the nanocrystalline silicon thin films deposited by capacitively coupled plasma.

• Transactions on Electrical and Electronic Materials
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• v.12 no.5
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• pp.197-199
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• 2011

In this paper, the bottom-gate thin-film transistors (TFTs) were fabricated with an amorphous/microcrystalline Si double layer (DL) as an active layer and the variations of the electrical characteristics were investigated according to the DC bias stresses. Since the fabrication process of DL TFTs was identical to that of the conventional amorphous Si (a-Si) TFTs, it creates no additional manufacturing cost. Moreover, the amorphous/microcrystalline Si DL could possibly improve stability and mass production efficiency. Although the field effect mobility of the typical DL TFTs is similar to that of a-Si TFTs, the DL TFTs had a higher reliability with respect to the direct current (DC) bias stresses.

• Proceedings of the KIEE Conference
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• 1998.07d
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• pp.1315-1317
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• 1998

We have investigated the effects of electrical stress on poly-Si TFTs with different hydrogen passivation conditions. The amounts of threshold voltage shift of hydrogen passivated poly-Si TFTs are much larger than those of as-fabricated devices both under the gate bias stressing and under the gate and drain bias stressing. Also, we have quantitatively analized the degradation phenomena using by analytical method. we have suggested that the electron trapping in the gate dielectric is the dominant degradation mechanism in only gate bias stressed poly-Si TFT while the creation of defects in the poly-Si is prevalent in gate and drain bias stressed device.

• Journal of the Korean Ceramic Society
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• v.29 no.1
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• pp.65-73
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• 1992

The effect of grain size on the time-dependent piezoelectrice degradation of a poled PZT of MPB composition Pb0.988Sr0.012 (Zr0.52Ti0.48)O3 with 2.4 mol% of Nb2O5 was studied, and the degradation mechanism was discussed. Changes in the internal bias field and the internal stress both responsible for the time-dependent degradation of poled PZT were examined by the polarization reveral technique, XRD and Vickers indentation, respectively. The piezoelectric degradation increased with increasing time and grain size, and the internal bias field due to space charge diffusion decreased with increasing grain size of poled PZT. The internal bias field, however, was almost insensitive to the degradation time regardless of the grain size. On the other hand, both the x-ray diffraction peak intensity ratio of (002) to (200) and the fracture behavior including the crack propagation support that the ferroelectric domain rearrangement of larger grain size showed rapid relaxation of the internal stress compared with smaller one, which is thought the origin of the larger piezoelectric degradation in the former. In conclusion, the contribution of space charge diffusion on the piezoelectric degradation of PZT is strongly dependent on both the grain size and the composition. Thus, the relaxation of internal stress due to the ferroelectric domain rearrangement as well as the amount and time-dependence of the internal bias field due to space charge diffusion should be considered simultaneously in the degradation mechanism of PZT.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.252-253
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• 2011

ZnO-based thin film transistors (TFTs) are of great interest for application in next generation flat panel displays. Most research has been based on amorphous indium-gallium-zinc-oxide (IGZO) TFTs, rather than single binary oxides, such as ZnO, due to the reproducibility, uniformity, and surface smoothness of the IGZO active channel layer. However, recently, intrinsic ZnO-TFTs have been investigated, and TFT- arrayss have been demonstrated as prototypes of flat-panel displays and electronic circuits. However, ZnO thin films have some significant problems for application as an active channel layer of TFTs; it was easy to change the electrical properties of the i-ZnO thin films under external conditions. The variable electrical properties lead to unstable TFTs device characteristics under bias stress and/or temperature. In order to obtain higher performance and more stable ZnO-based TFTs, HZO thin film was used as an active channel layer. It was expected that HZO-TFTs would have more stable electrical characteristics under gate bias stress conditions because the binding energy of Hf-O is greater than that of Zn-O. For deposition of HZO thin films, Hf would be substituted with Zn, and then Hf could be suppressed to generate oxygen vacancies. In this study, the fabrication of the oxide-based TFTs with HZO active channel layer was reported with excellent stability. Application of HZO thin films as an active channel layer improved the TFT device performance and bias stability, as compared to i-ZnO TFTs. The excellent negative bias temperature stress (NBTS) stability of the device was analyzed using the HZO and i-ZnO TFTs transfer curves acquired at a high temperature (473 K).

• Journal of the Korean Ceramic Society
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• v.47 no.6
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• pp.479-484
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• 2010

Microstructural and mechanical properties of the TiN films deposited on Si substrates under various substrate bias voltages by a reactive magnetron sputtering have been studied. It was found that the crystallographic texture, microstructural morphology and mechanical property of the TiN films were strongly depended on the substrate bias voltage. TiN films deposited without bias exhibited a mixed (200)-(111) texture with a strong (200) texture, which subsequently changed to a strong (111) texture with increasing bias voltage. It is also observed that the crystallite size decreases with increasing bias voltage, which corresponds to the increasing diffraction peak width of XRD patterns. The average surface roughness was calculated from AFM images of the films; these results indicated that the average surface roughness was increased with an increase in the bias voltage of the coatings.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.5
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• pp.519-525
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• 2015

Positive bias stress-induced instability in amorphous indium-gallium-zinc-oxide (a-IGZO) bottom-gate thin-film transistors (TFTs) was investigated under high $V_{GS}$/low $V_{DS}$ and low $V_{GS}$/high $V_{DS}$ stress conditions through incorporating a forward/reverse $V_{GS}$ sweep and a low/high $V_{DS}$ read-out conditions. Our results showed that the electron trapping into the gate insulator dominantly occurs when high $V_{GS}$/low $V_{DS}$ stress is applied. On the other hand, when low $V_{GS}$/high $V_{DS}$ stress is applied, it was found that holes are uniformly trapped into the etch stopper and electrons are locally trapped into the gate insulator simultaneously. During a recovery after the high $V_{GS}$/low $V_{DS}$ stress, the trapped electrons were detrapped from the gate insulator. In the case of recovery after the low $V_{GS}$/high $V_{DS}$ stress, it was observed that the electrons in the gate insulator diffuse to a direction toward the source electrode and the holes were detrapped to out of the etch stopper. Also, we found that the potential profile in the a-IGZO bottom-gate TFT becomes complicatedly modulated during the positive $V_{GS}/V_{DS}$ stress and the recovery causing various threshold voltages and subthreshold swings under various read-out conditions, and this modulation needs to be fully considered in the design of oxide TFT-based active matrix organic light emitting diode display backplane.

• 한국정보디스플레이학회:학술대회논문집
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• 2003.07a
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• pp.673-674
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• 2003

The reliability of TFT, crystallized by sequential lateral solidification (SLS) technology, has been studied High current damage is characterized by high gate bias (-20V) and drain bias (-10V). It is found that performance of SLS TFTs is enhanced by high current stress up to 300 sec of stress time for 20/8 (W/L) N-TFT. After that, TFT performance is degraded with the increase of the stress time. It is speculated from the experimental data that SLS TFTs initially contain a number of unstable defect states. Then, the defect states seem to be cured by high current stress.