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http://dx.doi.org/10.4313/TEEM.2011.12.5.197

Direct Current (DC) Bias Stress Characteristics of a Bottom-Gate Thin-Film Transistor with an Amorphous/Microcrystalline Si Double Layer  

Jeong, Tae-Hoon (School of Electrical and Electronic Engineering, Yonsei University)
Kim, Si-Joon (School of Electrical and Electronic Engineering, Yonsei University)
Kim, Hyun-Jae (School of Electrical and Electronic Engineering, Yonsei University)
Publication Information
Transactions on Electrical and Electronic Materials / v.12, no.5, 2011 , pp. 197-199 More about this Journal
Abstract
In this paper, the bottom-gate thin-film transistors (TFTs) were fabricated with an amorphous/microcrystalline Si double layer (DL) as an active layer and the variations of the electrical characteristics were investigated according to the DC bias stresses. Since the fabrication process of DL TFTs was identical to that of the conventional amorphous Si (a-Si) TFTs, it creates no additional manufacturing cost. Moreover, the amorphous/microcrystalline Si DL could possibly improve stability and mass production efficiency. Although the field effect mobility of the typical DL TFTs is similar to that of a-Si TFTs, the DL TFTs had a higher reliability with respect to the direct current (DC) bias stresses.
Keywords
Thin-film transistor; Double layer; Direct current (DC) bias stress; Reliability;
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