• 제목/요약/키워드: Bias pumping

검색결과 17건 처리시간 0.024초

Spiking Suppression of Quasi-continuous-wave Pulse Nd:YAG Laser Based on Bias Pumping

  • Chen, Yazheng;Wang, Fuyong
    • Current Optics and Photonics
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    • 제6권4호
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    • pp.400-406
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    • 2022
  • We numerically demonstrate that the inherent spiking behavior in the quasi-continuous-wave (QCW) operation of an Nd:YAG laser can be suppressed by adopting bias pumping. After spiking suppression, the output QCW pulses from a bias-pumped Nd:YAG laser are very stable, and they can maintain nearly the same temporal shape as that of pump pulse under different pump repetition rates and peak powers. Our study implies that bias pumping is an alternative method of spiking suppression in solid-state lasers, and the application areas of an Nd:YAG laser may be extended by bias pumping.

DRAM 의 저전력 구현을 위한 안정한 기판전압 발생기 설계에 관한 연구 (A study on the Design of a stable Substrate Bias Generator for Low power DRAM's)

  • 곽승욱;성양현곽계달
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 1998년도 추계종합학술대회 논문집
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    • pp.703-706
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    • 1998
  • This paper presents an efficient substrate-bias generator(SBG)for low-power, high-density DRAM's The proposed SBG can supply stable voltage with switching the supply voltage of driving circuit, and it can substitude the small capacitance for the large capacitance. The charge pumping circuit of the SBG suffere no VT loss and is to be applicable to low-voltage DRAM's. Also it can reduce the power consumption to make VBB because of it's high pumping efficiency. Using biasing voltage with positive temperature coefficient, VBB level detecting circuit can detect constant value of VBB against temperature variation. VBB level during VBB maintaining period varies 0.19% and the power dissipation during this period is 0.16mw. Charge pumping circuit can make VBB level up to -1.47V using VCC-1.5V, and do charge pumping operation one and half faster than the conventional ones. The temperature dependency of the VBB level detecting circuit is 0.34%. Therefore the proposed SBG is expected to supply a stable VBB with less power consumption when it is used in low power DRAM's.

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Pumping-up Current Characteristics of Linear Type Magnetic Flux Pump

  • Chung, Yoondo;Muta, Itsuya;Hoshino, Tsutomu;Nakamura, Taketsune;Ko, Taekuk
    • 한국초전도ㆍ저온공학회논문지
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    • 제6권2호
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    • pp.29-34
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    • 2004
  • The linear type flux pump aims to compensate a little bit decremental persistent current of the HTS magnet in NMR and MRI spectrometers. The flux pump mainly consists of DC bias coil, 3-phase AC coil and Nb foil. The persistent current in closed superconductive circuit can be easily adjusted by the 3-phase AC current, its frequency and the DC bias current. In the experiment, it has been investigated that the flux pump can effectively charge the current in the load coil of 543 mH for various frequencies in 18 minutes under the DC bias of 10 A and the AC of 5 $A_{rms}$. The maximum magnitudes of pumping current and load magnet voltage are 0.72 A/min and 20 ㎷, respectively. Based on simulation results by the FEM are proved to nearly agree with experimental ones.

Charge Pumping 기술을 응용한 열화된 SONOSFET 비휘발성 기억소자의 Si-SiO$_2$ 계면트랩에 관한 연구 (A Study on the Si-SiO$_2$Interface Traps of the Degraded SONOSFET Nonveolatile Memories with the Charge Pumping Techniques)

  • 김주열;김선주;이성배;이상배;서광열
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 1994년도 추계학술대회 논문집
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    • pp.59-64
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    • 1994
  • The Si-SiO$_2$interface trpas of the degraded short-channel SONOSFET memory devices were investigated using the charge pumping techniques. The degradation of devices with write/erase cycle appeared as the increase of the Si-SiO$_2$interface trap density. In order to determine the capture cross-section of the interface trap. I$\_$CP/-V$\_$GL/ characteristic curves were measured at different temperatures. Also, the spatial distributions of Si-SiO$_2$interface trap were examined by the variable-reverse bias boltage method.

한 쌍의 전극으로 전기 삼투 유동과 세포 분쇄 기능을 동시에 구현한 연속적인 세포 분쇄기 (A Continuous Electrical Cell Lysis Chip using a DC Bias Voltage for Cell Disruption and Electroosmotic Flow)

  • 이동우;조영호
    • 대한기계학회논문집A
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    • 제32권10호
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    • pp.831-835
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    • 2008
  • We present a continuous electrical cell lysis chip, using a DC bias voltage to generate the focused high electric field for cell lysis as well as the electroosmotic flow for cell transport. The previous cell lysis chips apply an AC voltage between micro-gap electrodes for cell lysis and use pumps or valves for cell transport. The present DC chip generates high electrical field by reducing the width of the channel between a DC electrode pair, while the previous AC chips reducing the gap between an AC electrode pair. The present chip performs continuous cell pumping without using additional flow source, while the previous chips need additional pumps or valves for the discontinuous cell loading and unloading in the lysis chambers. The experimental study features an orifice whose width and length is 20 times narrower and 175 times shorter than the width and length of a microchannel. With an operational voltage of 50 V, the present chip generates high electric field strength of 1.2 kV/cm at the orifice to disrupt cells with 100% lysis rate of Red Blood Cells and low electric field strength of 60 V/cm at the microchannel to generate an electroosmotic flow of $30{\mu}m/s{\pm}9{\mu}m/s$. In conclusion, the present chip is capable of continuous self-pumping cell lysis at a low voltage; thus, it is suitable for a sample pretreatment component of a micro total analysis system or lab-on-a-chip.

PMIC용 512비트 MTP 메모리 IP설계 (Design of a 512b Multi-Time Programmable Memory IPs for PMICs)

  • 장지혜;하판봉;김영희
    • 한국정보전자통신기술학회논문지
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    • 제9권1호
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    • pp.120-131
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    • 2016
  • 본 논문에서는 back-gate bias 전압인 VNN (Negative Voltage)을 이용하여 5V의 MV (Medium Voltage) 소자만 이용하여 FN (Fowler-Nordheim) tunneling 방식으로 write하는 MTP cell을 사용하여 512비트 MTP IP를 설계하였다. 사용된 MTP cell은 CG(Control Gate) capacitor, TG(Tunnel Gate) transistor와 select transistor로 구성되어 있다. MTP cell size를 줄이기 위해 TG transistor와 select transistor를 위한 PW(P-Well)과 CG capacitor를 위한 PW 2개만 사용하였으며, DNW(Deep N-Well)은 512bit MTP cell array에 하나만 사용하였다. 512비트 MTP IP 설계에서는 BGR을 이용한 voltage regulator에 의해 regulation된 V1V (=1V)의 전압을 이용하여 VPP와 VNN level detector를 설계하므로 PVT variation에 둔감한 ${\pm}8V$의 pumping 전압을 공급할 수 있는 VPP와 VNN 발생회로를 제안하였다.

PMOSFET의 채널 길이에 따른 NBTI 스트레스와 CHC 스트레스의 신뢰성 특성 비교 분석 (Comparative Analysis of Channel Length Dependence of NBTI and CHC Characteristics in PMOSFETs)

  • 유재남;권성규;신종관;오선호;;장성용;송형섭;이가원;이희덕
    • 한국전기전자재료학회논문지
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    • 제27권7호
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    • pp.438-442
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    • 2014
  • Channel length dependence of NBTI (negative bias temperature instablilty) and CHC (channel hot carrier) characteristics in PMOSFET is studied. It has been considered that HC lifetime of PMOSFET is larger than NBTI lifetime. However, it is shown that CHC degradation is greater than NBTI degradation for PMOSFET with short channel length. 1/f noise and charge pumping measurement are used for analysis of these degradations.

전하 전달 능력 향상 및 벌크 forward 문제를 개선한 CMOS 전하 펌프 (A Charge Pump with Improved Charge Transfer Capability and Relieved Bulk Forward Problem)

  • 박지훈;김정열;공배선;전영현
    • 대한전자공학회논문지SD
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    • 제45권4호
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    • pp.137-145
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    • 2008
  • 본 논문에서는 출력 단 전달 스위치로 NMOS와 PMOS를 병렬 결합하여 사용하고 벌크 펌핑 회로를 채용한 CMOS 전하펌프를 제안하였다. 제안된 전하 펌프는 NMOS 및 PMOS의 병렬 결합을 통하여 출력 단의 전류전달 능력을 향상시킬 수 있다. 또한, 채용된 벌크 펌핑 회로는 PMOS에 의한 벌크의 순방향 바이어스 문제를 효과적으로 해결할 수 있다. 제안된 회로의 성능을 확인하기 위하여, 80-nm CMOS 공정기술을 이용하여 전하 펌프를 설계하였다. 모사실험을 통한 비교 결과, 제안된 CMOS 전하 펌프는 기존의 NMOS 혹은 PMOS 만을 사용한 전하 펌프들과 비교하여 47% 이상의 전류전달 능력의 향상을 가져왔고 펌핑 속도도 9% 이상 개선되었으며, 동작 시 최대 벌크 순방향 전압 또한 24%이상 개선되어 벌크 순방향 바이어스 문제가 완화되었음을 확인하였다.

A High Performance Harmonic Mixer Using a plastic packaged device

  • ;;;신현식
    • 한국전자통신학회논문지
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    • 제2권1호
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    • pp.1-9
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    • 2007
  • In this paper, a third-order harmonic mixer is designed using frequency multiplier theory for the Ka-band. The gate bias voltage is selected by frequency multiplier theory to maximize the third-order harmonic element ofthe fundamental LO frequency in the proposed mixer. The designed mixer has a gate mixer structure composed of a gate terminal input for the fundamental local signal ($f_{LO}$), RF signal (${RF}$) and a drain terminal output for the harmonic frequency ($3f_{LO}-f_{RF}$) respectively. The Ka-band harmonic mixer is designed and fabricated using a commercial GaAs MESFET device with a plastic package. The proposed mixer will provide a solution for the problems found in the high cost, complex circuitry in a conventional Ka-band mixer. The 33.5 GHz harmonic mixer has a -10 dB conversion gain by pumping 11.5 GHz LO with a +5 dBm level.

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전계효과에 의한 칼코게나이드 박막에서의 광유기 복굴절 특성 (The Properties of Photoinduced Birefringence in Chalcogenide Thin Films by the Electric Field Effects)

  • 장선주;박종화;여철호;정홍배
    • 한국전기전자재료학회논문지
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    • 제14권1호
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    • pp.58-63
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    • 2001
  • We have investigated the photoinduced birefrinence by the electric field effects in chalcogenide thin films. The electric field effects have investigated the various applied bias voltages(forward and reverse) in chalcogenide thin films. A pumping (inducing) and a probing bean were using a linearly polarized He-Ne laser light (633nm) and semiconductor laser light (780nm), respectively. The result was shown that the birefringence had a higher value in DC +2V than the others, Also, we obtained the birefringence in the electric field effects by various voltages. In addition, we have discussed the anisotropy property of chalcogenide thin films by the electric field effects.

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