• The Journal of the Korea Contents Association
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• v.5 no.1
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• pp.229-236
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• 2005

Testing time and power consumption during testing System-On-a-Chip (SOC) are becoming increasingly important as the IP core increases in a SOC. We present a new algorithm to reduce the scan-in power and test data volume using the modified scan latch reordering. We apply scan latch reordering technique for minimizing the hamming distance in scan vectors. Also, during scan latch reordering, the don't care inputs in scan vectors are assigned for low power and high compression. Experimental results for ISCAS 89 benchmark circuits show that reduced test data and low power scan testing can be achieved in all cases.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.2
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• pp.145-153
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• 2001

As combinational ATPG algorithms achieve effectively 100% fault coverage, reducing the length of test set without loosing its fault coverage becomes a challenging work. The new approach is based on the independent and the compatible relationships between faults. For more compact test set, the size of compatible fault set must be maximized, thus this algorithm generates fault-pattern pairs, and a fault-pattern pair tree structure using the independent and the compatible relationships between faults. With the fault-pattern pair tree structure, a compact test set effectively generated. The experimental results for ISCAS 85 and 89 benchmark circuits demonstrate the effectiveness of the proposed method.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.3
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• pp.32-40
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• 2009

In order to reduce time-to-market, the demand for fast fault diagnosis has been increased. In this paper, a fault dropping technique with fault candidate ordering and test pattern ordering for fast fault diagnosis is proposed. Experimental results using the full-scanned ISCAS 89 benchmark circuits show the efficiency of the fault dropping technique with fault candidate ordering and test pattern ordering.

• Journal of the Korea Society of Computer and Information
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• v.22 no.3
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• pp.17-25
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• 2017

In this paper, we compared four analyzers Clang, CppCheck, Compass, and a commercial one from a domestic startup using the NIST's Juliet test suit and STONESOUP that is introduced recently. Tools showed detection efficacy in the order of Clang, CppCheck, the domestic one, and Compass under Juliet tests; and Clang, the domestic one, Compass, and CppCheck under STONESOUP tests. We expect it would be desirable to utilize symbolic execution for vulnerability analysis in the future. On the other hand, the results of tool evaluation also testifies that Juliet and STONESOUP as a benchmark for static analysis tools can reveal differences among tools. Finally, each analyzer has different CWEs that it can detect all given test programs. This result can be used for selection of proper tools with respect to specific CWEs.

• 전자공학회논문지 IE
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• v.45 no.3
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• pp.5-12
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• 2008

We propose efficient scan testing method capable of reducing the test data and power dissipation for digital logic circuits. The proposed testing method is based on a hybrid run-length encoding which reduces test data storage on the tester. We also introduce modified Bus-invert coding method and scan cell design in scan cell reordering, thus providing increased power saving in scan in operation. Experimental results for ISCAS'89 benchmark circuits show that average power of 96.7% and peak power of 84% are reduced on the average without fault coverage degrading. We have obtained a high reduction of 78.2% on the test data compared the existing compression methods.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.39B no.1
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• pp.1-7
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• 2014

This paper proposes an efficient test wrapper design that reduces overall test time in multi-core SoC. After initial local wrapper solution sets for all the cores are determined using well-known Combine algorithm, proposed algorithm selects a dominant core which consumes the longest test time in multi-core SoC. Then, the wrapper characteristics in the number of TAM wires and the test time for other cores are adjusted based on test time of the dominant core. For some specific cores, the number of TAM wires can be reduced by increasing its test time for design space exploration purposes. These modified wrapper characteristics are added to the previous wrapper solution set. By expanding previous local wrapper solution set to global wrapper solution set, overall test time for Multi-core SoC can be reduced by an efficient test scheduler. Effectiveness of the proposed wrapper is verified on ITC'02 benchmark circuits using $B^*$-tree based test scheduler. Our experimental results show that the test time is reduced by an average of 4.7% when compared to that of employing previous wrappers.

• The Journal of the Korea Contents Association
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• v.5 no.4
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• pp.188-196
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• 2005

This paper presents a new test data compression and low power scan test method that can reduce test time and power consumption. A proposed method can reduce the scan-in power and test data volume using a modified scan cell reordering algorithm and hybrid adaptive encoding method. Hybrid test data compression method uses adaptively the Golomb codes and run-length codes according to length of runs in test data, which can reduce efficiently the test data volume compare to previous method. We apply a scan cell reordering technique to minimize the column hamming distance in scan vectors, which can reduce the scan-in power consumption and test data. Experimental results for ISCAS 89 benchmark circuits show that reduced test data and low power scan testing can be achieved in all cases. The proposed method showed an about a 17%-26% better compression ratio, 8%-22% better average power consumption and 13%-60% better peak power consumption than that of previous method.

• Journal of Environmental Science International
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• v.25 no.4
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• pp.505-516
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• 2016

With the development of nanotechnology, nanomaterials are used in various fields. Therefore, the interest regarding the safety of nanomaterial use is increasing and much effort is diverted toward establishment of exposure assessment and management methods. Occupational exposure limits (OELs) are effectively used to protect the health of workers in various industrial workplaces. This study aimed to propose an OEL for domestic multi-walled carbon nanotubes (MWCNTs) based on animal inhalation toxicity test. Basic procedure for development of OELs was examined. For OEL estimation, epidemiological study and quantitative risk assessment are generally performed based on toxicity data. In addition, inhalation toxicity data-based no observed adverse effect level (NOAEL) and benchmark dose (BMD) are estimated to obtain the OEL. Three different estimation processes (NEDO in Japan, NIOSH in USA, and Baytubes in Germany) of OELs for carbon nanotubes (CNTs) were intensively reviewed. From the rat inhalation toxicity test for MWCNTs manufactured in Korea, a NOAEL of $0.98mg/m^3$ was derived. Using the simple equation for estimation of OEL suggested by NEDO, the OEL of $142{\mu}g/m^3$ was estimated for the MWCNT manufacturing workplace. Here, we used test rat and Korean human data and adopted 36 as an uncertainty factor. The OEL for MWCNT estimated in this work is higher than those ($2-80{\mu}g/m^3$) suggested by previous investigators. It may be greatly caused by different physicochemical properties of MWCNT and their dispersion method and test rat data. For setting of regulatory OELs in CNT workplaces, further epidemiological studies in addition to animal studies are needed. More advanced technical methods such as CNT dispersion in air and liquid should be also developed.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.1 s.343
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• pp.71-78
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• 2006

An NoC (Networks-on-Chip) is an emerging design paradigm intended to cope with a future SoC containing numerous built-in cores. In an NoC, the test strategy is very significant for its practicality and feasibility. Among existing test issues, TAM architecture and test scheduling will particularly dominate the overall test performance. In this paper, we address an efficient NoC test scheduling algorithm based on a rectangle packing approach used for an SoC test. In order to adopt the rectangle packing solution as an NoC test scheduling algorithm we design the configuration about test resources and test methods suitable for an NoC structure. Experimental results using some ITC'02 benchmark circuits show the proposed algorithm can reduce the overall test time by up to $55\%$ in comparison with previous works.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.11
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• pp.105-114
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• 2000

Delay testing is essential for assurance of digital circuits as the speed and the density of the circuits improve greatly. However, delay faults in sequential circuits cannot be detected easily due to the existence of state registers. To overcome this difficulty a new test method and algorithm are devised which can be used for both stuck-at testing and delay testing. To apply the new test method, a new scan flip-flop is implemented. Experimental results on ISCAS 89 benchmark circuits show that the number of testable paths can be increased drastically over conventional scan techniques.