• Proceedings of the KIEE Conference
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• 2002.07d
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• pp.2637-2639
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• 2002

This paper presents the design and implementation of a baseband Modem using DSP that supports a wireless LAN. It is implemented with DSP and D/A and A/D Converters in baseband and tested without using IF and RF modules. In this paper, we have used the matched filler and DLL(delay lock loop) for synchronization. And the matched filter and the carrier recovery are directly connected. Therefore, the proposed architecture is very simple and the operation of DSP becomes fast.

• Proceedings of the IEEK Conference
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• 2003.11c
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• pp.273-276
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• 2003

In this paper, we designed and made up/down converter (UDC) for using W-CDMA digital pre-distortion system which is one of the efficiency enhancement techniques. UDC is required that frequency up(baseband to RF) and down(RF to baseband) of information signals. The focus of the design and PCB layout is to satisfy the linearity of the UDC. We tested that UDC was satisfied specification which is based on 3GPP base stations and repeaters. The ACLR results which are -51.84dBc(Up Converter) and -55.0dBc(Down Converter) at upper 5 MHz offset from center-frequency show that UDC satisfy the 3GPP specification with superior linearity data.

• ETRI Journal
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• v.29 no.5
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• pp.596-606
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• 2007

It is well known that an OFDM receiver is vulnerable to synchronization errors. Despite fine estimations used in the initial acquisition, there are still residual synchronization errors. Though these errors are very small, they severely degrade the bit error rate (BER) performance. In this paper, we propose a residual error elimination scheme for the digital OFDM baseband receiver aiming to improve the overall BER performance. Three improvements on existing schemes are made: a pilot-aided recursive algorithm for joint estimation of the residual carrier frequency and sampling time offsets; a delay-based timing error correction technique, which smoothly adjusts the incoming data stream without resampling disturbance; and a decision-directed channel gain update algorithm based on recursive least-squares criterion, which offers faster convergence and smaller error than the least-mean-squares algorithms. Simulation results show that the proposed scheme works well in the multipath channel, and its performance is close to that of an OFDM system with perfect synchronization parameters.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 2004.11a
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• pp.258-258
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• 2004

• The Journal of the Korea institute of electronic communication sciences
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• v.8 no.11
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• pp.1641-1646
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• 2013

Control voltage for baseband channel selection filter to select one of communication channels can be easily fluctuated according to external noise or variation of fabrication. In this paper, we design a voltage regulator with small chip area to keep control voltage constantly using current comparative method. Cut-off frequency of channel selection filter is automatically controlled by detecting current flow using the proposed voltage regulator.

• Journal of Power Electronics
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• v.16 no.1
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• pp.388-397
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• 2016

An error-compensated pulse width modulator (ECPWM) is proposed to improve the baseband harmonic performance and the switching loss of voltage source inverters (VSIs). Selecting between harmonic distortion and switching loss is a design tradeoff in the conventional space vector pulse width modulation. In this work, an accumulated difference in produced and desired phase voltages is considered to adjust the reference signal. This mechanism can compensate for the voltage error in the previous carrier period. With error compensation every half-carrier period, the proposed ECPWM allows one-half reduction in carrier frequency without scarifying baseband harmonic distortion. The proposed modulator is applied to a three-phase VSI with R-L load and a motor-speed-control system for experiments. The measured efficiency and operating temperature of switches confirm the effectiveness of the proposed scheme.

• ETRI Journal
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• v.45 no.1
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• pp.150-162
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• 2023

The polar delta-sigma modulator (DSM) transmitter architecture exhibits good coding efficiency and can be used for software-defined radio applications. However, the necessity of high clock speed is one of the major drawbacks of using this transmitter architecture. This study proposes a low-complexity timeinterleaved architecture for the polar DSM transmitter baseband part to reduce the clock speed requirement of the polar DSM transmitter using an upsampling technique. Simulations show that using the proposed four-branch timeinterleaved polar DSM transmitter baseband part, the clock speed requirement of the transmitter is reduced by four times without degrading the signal-tonoise-and-distortion ratio.

• ETRI Journal
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• v.36 no.3
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• pp.352-360
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• 2014

This paper presents a 900 MHz zero-IF RF transceiver for IEEE 802.15.4g Smart Utility Networks OFDM systems. The proposed RF transceiver comprises an RF front end, a Tx baseband analog circuit, an Rx baseband analog circuit, and a ${\Delta}{\Sigma}$ fractional-N frequency synthesizer. In the RF front end, re-use of a matching network reduces the chip size of the RF transceiver. Since a T/Rx switch is implemented only at the input of the low noise amplifier, the driver amplifier can deliver its output power to an antenna without any signal loss; thus, leading to a low dc power consumption. The proposed current-driven passive mixer in Rx and voltage-mode passive mixer in Tx can mitigate the IQ crosstalk problem, while maintaining 50% duty-cycle in local oscillator clocks. The overall Rx-baseband circuits can provide a voltage gain of 70 dB with a 1 dB gain control step. The proposed RF transceiver is implemented in a $0.18{\mu}$ CMOS technology and consumes 37 mA in Tx mode and 38 mA in Rx mode from a 1.8 V supply voltage. The fabricated chip shows a Tx average power of -2 dBm, a sensitivity level of -103 dBm at 100 Kbps with PER < 1%, an Rx input $P_{1dB}$ of -11 dBm, and an Rx input IP3 of -2.3 dBm.

• Proceedings of the IEEK Conference
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• 2009.05a
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• pp.357-359
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• 2009

In this paper, the 2.4GHz doppler radar system consisting of the doppler radar module and a baseband module were designed to detect heartbeat and respiration signal without direct skin contact. A bio-radar system emits continuous RF signal of 2.4GHz toward human chest, and then detects the reflected signal so as to investigate cardiopulmonary activities. The heartbeat and respiration signals acquired from quadrature signal of the doppler radar system are applied to the pre-processing circuit, amplification circuit, and the offset circuit of the baseband module. ECG(electrocardiogram) and reference respiration signals are measured simultaneously to evaluate the doppler radar system. As a result, the respiration signal of doppler radar signal is detected to 1m without complex digital signal processing. The sensitivity and calculated from I/Q respiration signal were $98.29{\pm}1.79%$, $97.11{\pm}2.75%$, respectively, and positive predictivity were $98.11{\pm}1.45%$, $92.21{\pm}10.92%$, respectively. The sensitivity and positive predictivity calculated from phase and magnitude of the doppler radar were $95.17{\pm}5.33%$, $94.99{\pm}5.43%$, respectively. In this paper, we confirmed that noncontact real-time heartbeat and respiration detection using the doppler radar system has the possibility and limitation.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.34 no.1
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• pp.110-115
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• 2006

STSAT-2 is the first satellite which will be launched by the first Korean Space Launch Vehicle(KSLV). Ground station Baseband Control system(GBC) is now developed for STSAT-2. GBC has two functions. One is control data path between satellite control computers and ground station antennas(1.5M, 3.7M, 13M) automatically. The other is sending and receiving data between ground station and satellite. GBC is implemented by FPGA(Field-Programmable Gate Array) which includes almost all logic(for MODEM, PROTOCOL and GBC system control). MODEM in GBC has two uplink FSK modulators(1.2[kbps], 9.6[kbps]) and six downlink FSK demodulators(9.6[kbps], 38.4[kbps]). In hardware, STSAT-2 GBC is smaller than STSAT-1 GBC. In function, STSAT-2 GBC has more features than STSAT-1 GBC. This paper is about GBC structure, functions and test results.